Hard Mask Strained Silicon MOS Transistor Gate Protection
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Solution Overview
Problem
Conventional methods for manufacturing MOS devices face challenges in achieving smaller device sizes and faster switching speeds while maintaining clear signal transmission, requiring complex processes and structures that are difficult to manufacture and integrate.
Innovation Solution
The method involves forming strained silicon structures by depositing silicon germanium material into recessed regions adjacent to the channel region, using a hard mask to prevent deposition on the gate structure, thereby creating a compressively strained channel region, which enhances device performance without substantial modifications to conventional equipment or processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to manufacture MOS devices, then manufacturing processes and structures can be maintained, but device size reduction and switching speed improvement become difficult
Solution Approach 1:
A hard mask layer is deposited over the gate structure before source/drain formation to preemptively prevent silicon germanium material from depositing on the gate during subsequent deposition processes. This preliminary protective action eliminates the need for complex gate protection steps and ensures clean gate edges throughout manufacturing.
Solution Approach 2:
The hard mask layer serves as an intermediary barrier between the silicon germanium source/drain material and the gate structure. This intermediate layer prevents direct interaction that would cause material deposition on the gate, simplifying the overall manufacturing process while enabling advanced device features.
2Productivity
If device size is reduced to increase circuit density, then more devices can be fabricated per wafer, but signal clarity and manufacturing precision become more difficult to maintain
Solution Approach 1:
The hard mask is applied in advance before source/drain deposition to define precise gate boundaries. This preliminary masking ensures that even at reduced feature sizes (90nm and below), the gate structure remains clearly defined and protected, maintaining manufacturing precision throughout the scaling process.
Solution Approach 2:
The hard mask layer is a temporary, consumable protective layer that is deposited, serves its protective function during critical manufacturing steps, and is then removed. This disposable approach provides precise protection during source/drain formation without requiring permanent complex structures.
3Productivity
If silicon germanium material is deposited into source and drain regions to create strained silicon, then hole mobility improves, but gate structure contamination occurs
Solution Approach 1:
The hard mask layer is deposited over the gate structure before silicon germanium source/drain material deposition. This preliminary protection prevents any silicon germanium material from contaminating the gate structure, ensuring the gate remains substantially free from permanent deposition while still enabling strained silicon formation in the source/drain regions.
Solution Approach 2:
The hard mask acts as an intermediary barrier that allows silicon germanium material to be deposited into source/drain regions while preventing the same material from depositing on the gate structure. This intermediary protection maintains gate purity while enabling the mobility-enhancing strained silicon configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device yields, maintains compatibility with existing technology, and improves hole mobility for CMOS devices, particularly at design rules of 90 nanometers and below, while simplifying the manufacturing process.
Implementation Method 1
depositing silicon germanium material into the source region and the drain region
Implementation Method 2
using a hard mask to prevent deposition on the gate structure
Implementation Method 3
creating a compressively strained channel region
Data Source
AI summary
A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.