Semiconductor Hard Mask Patterning for Sub-20 Nm CD Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in achieving high etch selectivity and preserving critical dimensions during the fabrication of semiconductor devices, particularly in forming small features with high aspect ratios, where traditional methods often result in defects and reduced process windows.

Innovation Solution

The use of atomic layer deposition (ALD) to form hard mask features one layer at a time, combined with plasma treatment, to enhance etch selectivity and maintain high aspect ratios, allowing for the formation of smaller features without defects by utilizing materials like SiOx, SiCxOy, SiN, TiO, Al2O3, or TiN, and applying precursors such as tris(dimethylamino)silane and reaction gases like Ar, O2, and N2O, while keeping the deposition temperature below 300°C to prevent material decomposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional photolithographic exposure is used, then manufacturing process is simple, but resolution is insufficient for sub-20 nm features

Engineering Contradiction:
Improvefeature resolutionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies multi-patterning techniques that divide the patterning process into multiple discrete steps, including multiple photolithographic exposures and etching cycles. Each step creates a portion of the final pattern, allowing sub-20 nm features to be formed by sequentially building complexity rather than attempting to create all features in a single exposure step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary patterning actions where initial patterns are formed using photolithography and etching to create mandrels or spacers. These preliminary structures serve as templates for subsequent patterning steps, enabling the formation of finer features by using previously created structures as guides for additional material deposition and removal.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If feature size is reduced to increase integration density, then more components fit in given area, but etch selectivity and critical dimension preservation become difficult

Engineering Contradiction:
Improveintegration densityVSAvoidcritical dimension preservation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent utilizes parameter changes in the etching process, including adjusting etch chemistry, temperature, pressure, and power levels, to optimize etch selectivity between different materials. By dynamically changing process parameters during multi-step etching sequences, the patent maintains precise control over critical dimensions even as feature sizes are reduced to increase integration density.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures with multiple layers having different etch selectivities, such as combining silicon nitride, silicon oxide, and various metal layers. These composite structures allow differential etching where each material layer can be selectively removed or modified, enabling precise control over critical dimensions during the scaling process.

Inventive Principle:
Principle #40Composite materials

3Manufacturing precision

If multi-patterning is used to achieve sufficient resolution, then sub-20 nm features can be formed, but process complexity and number of steps increase

Engineering Contradiction:
Improvefeature resolutionVSAvoidprocess time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges multiple patterning operations into integrated process flows where photolithography, etching, and material deposition steps are combined and overlapped. By merging sequential operations into parallel or overlapping process sequences, the patent reduces the total time required for multi-patterning while maintaining the resolution benefits of multiple patterning steps.

Inventive Principle:
Principle #5Merging (Combining)

4Manufacturing precision

If deposition temperature is increased to improve film quality, then material properties improve, but material decomposition occurs above 300°C

Engineering Contradiction:
Improvefilm qualityVSAvoidmaterial decomposition
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes deposition parameters including using atomic layer deposition (ALD) at controlled temperatures below 300°C, adjusting precursor flow rates, and modifying chamber pressure to achieve high-quality films without thermal decomposition. By optimizing the combination of temperature, pressure, and precursor delivery parameters, the patent maintains film quality while avoiding material degradation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of smaller features with reduced end-to-end distances between conductive lines, increasing the process window and preventing pattern failure by maintaining high etch selectivity and critical dimension preservation, thus improving the manufacturing process for semiconductor devices.

Implementation Method 1

Atomic layer deposition (ALD) is a thin-film deposition technique based on the sequential use of a gas phase chemical process. ALD is a subclass of chemical vapor deposition. The majority of ALD reactions use two chemicals, typically called precursors. These precursors react with the surface of a material one at a time in a sequential, self-limiting, manner.

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

performing a plasma treatment on the gap-filling material

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS11854798B2Semiconductor device and method
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11854798B2 patent drawing
  • US11854798B2 patent drawing
  • US11854798B2 patent drawing

AI summary

A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.