Hard Mask Stack for Precise Trench and Via Patterning
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Solution Overview
Problem
As integrated circuits scale down, features transferred to hard mask layers often break down during etching processes, leading to defects and low-quality features in target layers, necessitating improved hard mask layers and patterning methods.
Innovation Solution
A hard mask stack comprising two dielectric mask layers with high etch selectivity and a metal-containing mask layer is used, where the dielectric layers have different etch properties, enabling precise patterning and etching without damaging the conductive lines and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-layer hard mask is used, then manufacturing process is simple, but features break down during etching leading to defects
Solution Approach 1:
The hard mask is divided into multiple layers (first hard mask layer, second hard mask layer, third hard mask layer) with different materials and etch selectivities. Each layer serves a specific function in the etching process, preventing feature breakdown while maintaining manufacturing feasibility through systematic division of the mask structure.
Solution Approach 2:
The patent uses composite material structure combining different dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride) with distinct etch selectivities. This composite approach allows selective etching of each mask layer with appropriate chemistry, improving feature quality during the etching process.
2Productivity
If pitch is reduced to increase integration density, then more components fit in chip area, but feature breakdown increases during etching
Solution Approach 1:
By segmenting the hard mask into multiple layers with progressive etching, the patent enables precise control of pattern transfer at reduced pitches. Each layer is etched selectively, maintaining feature integrity even at higher integration densities where features are more densely packed and vulnerable to breakdown.
Solution Approach 2:
The patent changes material parameters by selecting dielectric layers with different etch selectivities and physical properties. This allows optimization of etching conditions for each layer, enabling precise patterning at reduced pitch while maintaining feature integrity through controlled material removal.
3Manufacturing precision
If aggressive etching is used to maintain feature definition, then pattern transfer is precise, but conductive lines and vias are damaged
Solution Approach 1:
The patent places protective hard mask layers over conductive lines and vias before etching. These layers act as a cushion or barrier that prevents direct contact between aggressive etchants and sensitive conductive structures, allowing precise pattern transfer without damaging underlying features.
Solution Approach 2:
The hard mask layers serve as intermediary structures between the etching process and the conductive features. They mediate the interaction by providing a controlled interface that allows precise pattern definition while protecting sensitive conductive elements from harmful etching effects.
Data Source
AI summary
Embodiments of the present disclosure relates to method of forming trench and via features using dielectric and metal mask layers. Particularly, embodiments of present disclosure provide a hard mask stack including a first dielectric mask layer, and second dielectric mask layer and a metal mask layer, wherein the first dielectric mask layer and second dielectric mask layer have a high etch selectivity.