Hard-Saturation Linear Amplifier With Impedance-Transformed Load
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Solution Overview
Problem
Existing high power field-effect transistor (FET) amplifiers require trade-offs between efficiency and linearity and typically use multiple FETs, which complicates their design and operation.
Innovation Solution
The design employs a single FET or Bipolar Junction Transistor (BJT) with 'hard saturation' characteristics, combined with specific bias voltage and load resistance combinations that maintain the drain or collector voltage above the saturation voltage but below the breakdown voltage, utilizing impedance transforming networks to ensure linearity and high efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple FETs are used to achieve high power and improved linearity, then linearity and power are improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions (high power amplification and linearity improvement) into a single FET device by utilizing the device's inherent hard saturation characteristics. This eliminates the need for separate FETs dedicated to different functions, thereby reducing device complexity while maintaining linearity and power performance.
Solution Approach 2:
The single FET is designed to perform multiple functions simultaneously: it provides high power amplification, maintains linearity through hard saturation operation, and achieves high efficiency. The impedance transforming network enables this multi-functionality by presenting optimal load conditions across the entire signal cycle.
2Reliability
If multiple FETs are used in predistortion or out-phasing architectures, then linearity is improved, but efficiency deteriorates due to trade-offs
Solution Approach 1:
The patent changes the operating parameters of the FET by utilizing its hard saturation characteristics and optimizing the bias voltage and load resistance values. This allows the device to operate in a regime where both linearity and efficiency are improved simultaneously, eliminating the need for trade-offs required in conventional multi-FET architectures.
Solution Approach 2:
The impedance transforming network acts as an intermediary that presents optimal load conditions to the FET, enabling it to operate in the hard saturation region throughout the entire signal cycle. This intermediary component allows the FET to maintain both linearity and high efficiency without requiring complex multi-FET configurations.
3Power
If FET operates at maximum output power, then power is improved, but linearity deteriorates due to deviation from hard saturation
Solution Approach 1:
The patent employs dynamic impedance transformation that adapts to the FET's operating conditions throughout the signal cycle. The impedance transforming network dynamically presents the optimal load resistance that maintains hard saturation operation even at maximum output power, thereby preserving linearity while maximizing power output.
Solution Approach 2:
The bias network is configured in advance to provide the optimal bias voltage that positions the FET operating point in the hard saturation region. This preliminary configuration ensures that the FET maintains linear operation throughout the entire signal cycle, including at maximum output power conditions.
Data Source
AI summary
An amplifier includes a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT) with “hard saturation.”; where the FET or the BJT to has a nearly constant drain or collector current when the drain or collector voltage is greater than the pinchoff voltage. The amplifier further includes a bias network, configured to provide a DC voltage to the FET or the BJT, a means for isolating the DC voltage from the matching network, an electrical load, and a matching network which transforms the electrical load to a resistance between the drain and the source or the collector and emitter which causes the drain or collector voltage to be greater than the pinchoff voltage over the entire cycle of the sinusoidal voltage applied to the gate, whereby the amplifier is linear.