Hardened DSP Circuits in Programmable Logic for Lower Power
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Solution Overview
Problem
Programmable integrated circuits (ICs) face challenges in conserving resources and reducing power consumption due to thermal and die size limitations, particularly when implementing frequently performed digital signal processing functions, which hinders integration and efficiency.
Innovation Solution
The implementation of hardened circuits within programmable devices, which have predetermined functionalities, in conjunction with configurable logic, allows for efficient digital signal processing by separating common functions from customizable ones, thereby optimizing resource usage and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all digital signal processing functions are implemented using programmable logic, then functionality and flexibility are improved, but resource consumption and power usage increase
Solution Approach 1:
The patent segments digital signal processing functions into two categories: frequently performed functions implemented as hardened circuits and customizable functions implemented as programmable logic. This segmentation allows the system to optimize resource usage by dedicating hardware resources to common functions while maintaining flexibility for specialized functions through programmable logic.
Solution Approach 2:
The patent applies local quality by providing different implementation approaches for different functions within the same device. Hardened circuits provide fixed, efficient implementation for common functions, while programmable logic blocks provide configurable implementation for specialized functions, allowing each part of the system to have the appropriate quality for its specific purpose.
2Adaptability or versatility
If frequently performed functions are implemented using programmable logic, then functionality is improved, but resource consumption increases due to thermal and die size limitations
Solution Approach 1:
The patent segments the device into hardened circuit regions for frequently performed functions and programmable logic regions for customizable functions. This segmentation conserves programmable fabric resources by implementing common functions in dedicated hardware, thereby reducing the quantity of programmable resources required while maintaining overall functionality.
Solution Approach 2:
The hardened circuits provide universal implementation for frequently performed digital signal processing functions across multiple applications. By creating multi-functional hardened blocks that can handle common operations, the patent reduces the need for redundant programmable logic instances, thereby conserving resources.
3Adaptability or versatility
If more functions are implemented in programmable fabric, then versatility is improved, but integration is hindered due to thermal and die size limitations
Solution Approach 1:
The patent segments the device architecture into dedicated hardened circuit blocks and programmable logic blocks with separate interconnect structures. This segmentation allows for more efficient layout and routing, reducing interconnect complexity and improving integration by clearly defining the roles and connections of different functional blocks.
Data Source
AI summary
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.