Metal Hardmask Sidewall Modification for Void-Free Interconnect Fill
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Solution Overview
Problem
Voids in dual damascene interconnects increase electrical resistance and reduce the reliability and clock speed of integrated circuits due to non-uniform seed layer deposition during electroplating, which is sensitive to obstructions and diffusion rates in the manufacturing process.
Innovation Solution
Modifying the metal hardmask by diffusing non-metal atoms, such as nitrogen, to create a poisoned layer with sloped sidewalls, which promotes uniform seed layer deposition and reduces the formation of voids by eliminating constriction points in the interconnect openings, thereby ensuring a more uniform and void-free bulk conductive material fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electroplating is used to fill interconnect openings, then bulk conductive material is deposited, but non-uniform seed layer deposition occurs due to obstructions and diffusion rates, resulting in void formation
Solution Approach 1:
The patent modifies the sidewall surface properties by introducing a gradient structure with varying surface energies or compositions (e.g., through plasma treatment, chemical modification, or layered coating with different affinities). This parameter change ensures uniform seed layer deposition by eliminating preferential accumulation zones, thereby preventing void formation during electroplating
Solution Approach 2:
The patent introduces an intermediary layer or surface modification (such as a plasma-treated layer or chemically modified sidewall) that mediates between the original sidewall and the seed layer. This intermediary ensures uniform nucleation and growth of the seed layer by providing consistent surface properties, eliminating the non-uniform deposition that leads to voids
2Productivity
If dual damascene interconnects are manufactured with conventional methods, then interconnect structures are formed, but voids increase electrical resistance and reduce clock speed
Solution Approach 1:
The patent performs preliminary modification of the interconnect opening sidewalls before seed layer deposition and electroplating. This preliminary action (surface treatment, gradient structure creation, or intermediary layer formation) ensures that subsequent material deposition is uniform, preventing void formation that would otherwise increase electrical resistance and reduce clock speed
Solution Approach 2:
The patent changes physical or chemical parameters of the sidewall surface (such as surface energy, roughness, or composition gradient) to optimize seed layer deposition uniformity. This parameter change ensures complete, void-free filling during electroplating, thereby minimizing electrical resistance and maximizing clock speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in reduced resistance and improved switching times for integrated circuits by minimizing voids in interconnect structures and enhancing the uniformity of seed layer deposition, leading to more reliable and efficient semiconductor device manufacturing.
Implementation Method 1
modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask
Implementation Method 2
non-uniform seed layer deposition during electroplating
Data Source
AI summary
A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. Th method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.