Self-limited Planarization of Hardmask Spacers
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Solution Overview
Problem
In substrate processing systems, the asymmetric shape of spacers formed during anisotropic etching leads to increased variability in critical dimension (CD) transfer, particularly in double patterning approaches, resulting in inconsistent mask shapes that complicate subsequent pitch splitting processes.
Innovation Solution
A self-limited planarization method is employed, involving the deposition of a conformal layer, partial etching to create spacers with an asymmetric profile, followed by selective etching of cores and polymer film deposition on spacer sidewalls, and subsequent etching to remove the asymmetric profile and planarize the spacers, using a substrate processing chamber with controlled pressure and fluorine-based etch gas mixtures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If anisotropic etching is used to create spacers, then the spacers are formed with defined critical dimensions, but the upper portions of the spacers have an asymmetric profile that increases CD transfer variability
Solution Approach 1:
A conformal layer is deposited on the substrate before etching to define the spacer profile. This preliminary conformal deposition establishes a symmetric baseline structure that compensates for the asymmetric ion sputtering that will occur during subsequent anisotropic etching, ensuring that the final spacer has a symmetric upper portion suitable for direct mask reuse
Solution Approach 2:
The etching process parameters are optimized to control the degree of ion sputtering and achieve the desired asymmetric profile modification. By adjusting etch gas composition, pressure, and power parameters, the process transforms the initially symmetric conformal layer into spacers with controlled asymmetric profiles that can be subsequently planarized
2Productivity
If the asymmetric spacer profile is used directly for mask transfer, then the process is simpler, but the CD transfer variability increases and mask shape consistency deteriorates
Solution Approach 1:
The spacer formation process is segmented into distinct stages: conformal layer deposition, anisotropic etching to create asymmetric profile, and selective planarization. This segmentation allows each stage to be optimized independently, achieving both process efficiency and high precision CD transfer by addressing the asymmetric profile issue in a dedicated planarization step rather than requiring complete process redesign
Solution Approach 2:
A polymer film is deposited as an intermediary protective layer on the spacer sidewalls during the planarization etch process. This intermediary layer protects the asymmetric portions that need to be removed while preserving the symmetric upper portions, enabling precise control of the spacer profile for consistent mask transfer
3Manufacturing precision
If additional pitch splitting is performed to create squared mask shape, then the mask shape consistency is improved, but the process complexity and number of steps increases
Solution Approach 1:
The planarization process is designed to be self-limiting, where the etching automatically stops when the symmetric upper portion of the spacer is achieved. The polymer film intermediary and controlled etch parameters enable the process to self-regulate, eliminating the need for additional pitch splitting steps while maintaining high mask shape consistency and reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces CD transfer variability by creating symmetric, square-shaped masks, allowing for direct reuse in subsequent pitch splitting without transferring the mask to another layer, and can be applied to modify other asymmetric structures, ensuring consistent and reliable patterning results.
Implementation Method 1
supplying an etch gas mixture including fluorine-based gas to the upper chamber region
Implementation Method 2
an inductive coil arranged outside of the upper chamber region
Implementation Method 3
supplying RF bias power to the substrate support in a range from 50 W to 1000 W during f)
Implementation Method 4
ion sputtering during the anisotropic etching
Implementation Method 5
depositing polymer film on sidewalls of the spacers
Data Source
AI summary
A method for processing a semiconductor substrate includes a) providing a substrate stack including a first layer, a plurality of cores arranged in a spaced relationship on the first layer and one or more underlying layers arranged below the first layer; b) depositing a conformal layer on the first layer and the plurality of cores; c) partially etching the conformal layer to create spacers arranged adjacent to sidewalls of the plurality of cores, wherein the partial etching of the conformal layer causes upper portions of the spacers to have an asymmetric profile; d) selectively etching the plurality of cores relative to the spacers and the first layer; e) depositing polymer film on sidewalls of the spacers; and f) etching the upper portions of the spacers to remove the asymmetric profile and to planarize the upper portions of the spacers.