Hardware-Accelerated Instruction Mapping via Constraint Satisfaction
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Solution Overview
Problem
Existing techniques for implementing computations using hardware-accelerated instructions face challenges in automatically determining optimal invocations, leading to inefficient use of hardware resources due to complex dataflows and reliance on explicit transformations, which can result in missed implementation opportunities and increased search spaces.
Innovation Solution
The approach formulates the problem of determining hardware-accelerated instruction invocations as a constraint satisfaction problem, using data flow and input constraints to progressively construct mappings between computation and instruction data flow graphs, allowing for flexible memory layouts and implicit implementation decisions, thereby finding more efficient invocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If loop-level representation of operators is used with explicit IR transformations, then code generation can be performed, but implementation decisions are implicitly restricted and possible implementations may be missed
Solution Approach 1:
The patent inverts the conventional approach by not starting with loop-level representations and transformations, but rather by directly working with tensor access functions and hardware instruction mappings. This inversion allows the system to explore implementations without being constrained by predetermined loop structures and transformation sequences, thereby finding more implementation possibilities including those that would be missed by traditional approaches.
2Adaptability or versatility
If a large set of IR transformations is used to explore implementation space, then more solutions may be found, but the search space increases with diminishing returns
Solution Approach 1:
The patent extracts and focuses on the essential elements for implementation mapping: tensor access functions, hardware instruction characteristics, and data flow requirements. By taking out the non-essential loop-level transformation details and concentrating on the core mapping problem, the system achieves effective implementation exploration without the combinatorial explosion of a large transformation set.
Solution Approach 2:
The patent changes the parameters of the search problem from loop-level transformation sequences to tensor access function mappings. This parameter change transforms the search space from a complex sequence of transformations to a more manageable space of access function configurations, reducing search complexity while maintaining the ability to find optimal implementations.
3Measurement precision
If pattern matching is used to match tensor access functions, then some implementations can be found, but matches are difficult to establish in general cases
Solution Approach 1:
The patent creates a universal matching framework that works across different access function types without requiring specialized pattern matching for each case. By formulating a general algorithm that handles various access patterns through unified principles, the system achieves both accuracy in matching and simplicity in implementation, avoiding the complexity of multiple specialized pattern matchers.
Data Source
AI summary
A computer-implemented method of implementing a computation using a hardware-accelerated instruction of a processor system by solving a constraint satisfaction problem. A solution to the constraint satisfaction problem represents a possible invocation of the hardware-accelerated instruction in the computation. The constraint satisfaction problem assigns nodes of a data flow graph of the computation to nodes of a data flow graph of the instruction. The constraint satisfaction problem comprises constraints enforcing that the assigned nodes of the computation data flow graph have equivalent data flow to the instruction data flow graph, and constraints restricting which nodes of the computation data flow graph can be assigned to the inputs of the hardware-accelerated instruction, with restrictions being imposed by the hardware-accelerated instruction and/or its programming interface.