Hardware-Accelerated Memory Read-Level Selection Under Charge Loss

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Solution Overview

Problem

Conventional memory systems face challenges in accurately reading data due to charge loss in memory cells, leading to increased read errors and inefficiencies in determining optimal read levels, particularly in higher density memory devices, which results in higher computational demands and energy consumption.

Innovation Solution

The method involves determining optimal read levels using a limited subset of memory cells with known reference data, employing a hardware accelerator to sweep read levels and calculate error counts, thereby bypassing iterative read levels and error correction codes to reduce computational load and energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional iterative read levels and error correction codes are used to determine optimal read levels, then read accuracy can be maintained, but computational load and energy consumption increase significantly

Engineering Contradiction:
Improveread accuracyVSAvoidenergy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts the read level determination process from the main data read path by using a separate calibration region containing reference data. This allows optimal read levels to be determined independently using a hardware accelerator, avoiding the need to process actual user data through complex iterative algorithms and error correction codes, thereby reducing energy consumption while maintaining read accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs read level calibration in advance by storing known reference data in a dedicated calibration region. The hardware accelerator uses this pre-prepared reference data to determine optimal read levels before actual data reading operations, eliminating the need for computationally intensive iterative processes during normal read operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If iterative read levels and error correction codes are employed to compensate for charge loss, then read errors can be corrected, but computational complexity increases

Engineering Contradiction:
Improveread error rateVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a hardware accelerator as an intermediary component specifically designed to perform read level determination. This dedicated hardware unit handles the computational complexity of analyzing voltage distributions and determining optimal read levels, separating this complex task from the main memory controller and reducing overall system computational burden while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent uses reference data that is a known copy or representation of expected memory cell states stored in a calibration region. By comparing actual reads against this known reference, the system can determine optimal read levels without needing to perform complex error correction on actual user data, simplifying the computational process while maintaining read accuracy.

Inventive Principle:
Principle #26Copying

3Measurement precision

If a large number of memory cells are scanned to determine optimal read levels, then accuracy improves, but time consumption increases

Engineering Contradiction:
Improveread level determination accuracyVSAvoidtime consumption
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the memory device into a calibration region containing reference data and a main data region. The read level determination process is performed separately on the calibration region using a hardware accelerator, which can quickly analyze the known reference patterns. This segmentation allows accurate read level determination without scanning the entire memory array, significantly reducing time consumption while maintaining accuracy.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250292860A1Determining read levels using reference data
Publication Date: 2025.09.18 MICRON TECHNOLOGY INC
  • US20250292860A1 patent drawing
  • US20250292860A1 patent drawing
  • US20250292860A1 patent drawing

AI summary

Methods, systems, and apparatuses include retrieving reference data for a memory device. A read margin is scanned by determining sense data and pre-sense data for read levels of the read margin by applying a threshold voltage at each read level to cells of the memory device. A total error count is calculated by the memory device for each read level using the sense data, the pre-sense data, and the reference data. An optimal read level is selected for the read margin in response to comparing the total error count for each read level and determining a read level that has a lowest total error count.