Hardware-Accelerated Resource Tiling for Sparse Data Memory
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Solution Overview
Problem
Hardware-accelerated games and applications with large content surfaces, such as scrollable interfaces or terrain environments, face impractical memory usage since only a small fraction of the content is visible at any given time, making it inefficient to reserve physical memory for the entire surface.
Innovation Solution
Implementing a logical resource using a physical tile pool for sparse data sets, where the graphics processing unit allocates memory into a primary physical tile pool and selectively maps logical tiles to physical tiles, allowing for efficient storage and access of sparse data sets without direct one-to-one mapping, enabling resizing of the tile pool as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If physical memory is reserved for the entire content surface, then the application can access any part of the content, but memory usage becomes impractical since only a small fraction is visible at any given time
Solution Approach 1:
The content surface is divided into discrete tiles that can be independently managed. Instead of loading the entire content surface into memory, only the tiles that are currently visible or needed are allocated and mapped, allowing selective memory usage while maintaining access to the full content space.
Solution Approach 2:
The patent introduces a logical tile space that is decoupled from physical memory allocation. This creates an additional dimension of abstraction where logical tiles can be addressed in a continuous coordinate space while physical memory is allocated sparsely, resolving the contradiction between continuous content access and discrete memory usage.
2Quantity of substance
If the content surface is divided into discrete tiles for memory efficiency, then memory usage is optimized, but seams may appear between tiles during rendering
Solution Approach 1:
The hardware-accelerated tiling system acts as an intermediary layer between the logical tile space and physical memory. This intermediary handles tile mapping, blending, and coordinate transformations seamlessly, ensuring that the discrete tiled structure is invisible to the application and no seams appear in the rendered output.
3Device complexity
If a one-to-one mapping is used between logical and physical tiles, then memory allocation is simplified, but flexibility to resize and manage tile pools is reduced
Solution Approach 1:
The tile mapping system is designed to be dynamic rather than static. The hardware tiling infrastructure supports runtime changes to tile pool sizes, mapping configurations, and content dimensions without requiring system reconfiguration. This allows the system to adapt to different content sizes and memory conditions while maintaining efficient tile management.
Data Source
AI summary
In one embodiment, a graphics processing unit 170 may support a logical resource using a physical tile pool 350 for sparse data sets. The graphics processing unit 170 may allocate a physical memory allocation into a primary physical tile pool 350. The graphics processing unit 170 may define a mapping for a logical tile set 300 for a logical resource. The graphics processing unit 170 may selectively map a primary logical tile 320 of the logical tile set 300 to a primary physical tile 360 of the primary physical tile pool 350.