Hardware Accelerator for Authenticated Encryption Throughput
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Solution Overview
Problem
Current hardware implementations for encryption operations, such as those using the ChaCha and Blake standards, face performance limitations when executed solely in software or micro-code, lacking the throughput and efficiency required for high-speed cryptographic applications.
Innovation Solution
A configurable hardware accelerator is designed to perform encryption operations using dedicated circuitry for ChaCha and Blake standards, incorporating delayed column/diagonal state alignment techniques, allowing for optimized data paths and flexible operation across various rounds, thereby enhancing performance and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If encryption operations are executed in software or micro-code, then device complexity is reduced, but processing speed and throughput are insufficient for high-speed cryptographic applications
Solution Approach 1:
The encryption operation is divided into multiple quarter-round operations that can be executed in parallel. Each quarter-round processes a specific subset of state variables, allowing simultaneous execution across multiple hardware units to achieve high throughput while maintaining modular circuit design.
Solution Approach 2:
The patent transitions from sequential software execution to parallel hardware execution by organizing the encryption state as a 4x4 matrix and processing multiple state elements simultaneously across different spatial dimensions in the hardware circuit, dramatically increasing throughput.
2Productivity
If dedicated hardware circuitry is implemented for ChaCha and Blake standards, then encryption throughput increases significantly, but device complexity and chip area increase
Solution Approach 1:
The hardware accelerator is designed with a unified circuit structure that can perform multiple cryptographic functions including ChaCha20 encryption, Blake hash functions, and different round configurations. This multi-functional design achieves high throughput for various operations while sharing common hardware resources to minimize chip area.
Solution Approach 2:
The patent combines the ChaCha quarter-round logic and Blake round logic into a unified hardware circuit that can be configured for different operations. By merging these functions into a single accelerator unit with shared resources, the design achieves high productivity while reducing overall chip area compared to separate dedicated circuits.
3Adaptability or versatility
If variable rounds and cryptographic hash functions are supported, then adaptability increases, but device complexity and configuration overhead increase
Solution Approach 1:
The hardware accelerator incorporates dynamic configuration capabilities that allow the circuit to be reconfigured at runtime to support different cryptographic standards (ChaCha, Blake), different round counts, and different operation modes. This dynamic adaptability is achieved through control logic that adjusts circuit behavior based on input parameters without requiring physical reconfiguration.
Data Source
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AI summary
Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.