Hardware Accelerator Bloom Filter Partitioning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Modern databases face computational challenges in handling large datasets and complex queries, leading to expensive operations, particularly in filtering large datasets without increasing the false positive rate.

Innovation Solution

The implementation of hardware-accelerated data filtering using a distributed Bloom filter across multiple hardware accelerators, where bit vectors are partitioned across these accelerators, allowing for efficient filtering without explicit data partitioning and reducing the host's logic complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data filtering is performed using traditional software-based methods, then the host processor can handle complex queries, but the computational cost and processing time increase significantly for large datasets

Engineering Contradiction:
Improvedata filtering speedVSAvoidcomputational cost
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the filtering task into multiple segments by distributing data across multiple hardware accelerators, each processing a portion of the dataset in parallel. This segmentation enables simultaneous processing of multiple data chunks, dramatically improving filtering speed while reducing the computational burden on any single processor unit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces hardware accelerators as intermediary devices between the host processor and the data storage. These accelerators offload the computationally intensive filtering operations from the host processor, allowing the host to focus on higher-level query management while the hardware accelerators handle the heavy lifting of data filtering.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If bit vectors are distributed across multiple hardware accelerators, then filtering capacity increases for large datasets, but the system complexity increases

Engineering Contradiction:
Improvefiltering capacityVSAvoidsystem complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent combines multiple hardware accelerators into a unified filtering system where each accelerator maintains a portion of the bit vectors. The accelerators work together as a coordinated ensemble, with the host processor managing the distributed bit vector structure. This merging approach increases filtering capacity while the standardized interface and coordinated control mechanisms keep system complexity manageable.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If traditional filtering methods are used, then the host processor maintains full control, but bandwidth utilization is insufficient for handling large datasets efficiently

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidprocessing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-computing hash values and organizing data into structured formats before the actual filtering operation. Hardware accelerators pre-load and pre-process data segments, preparing them for rapid filtering. This preliminary preparation enables more efficient use of available bandwidth during the filtering operation and reduces the time required for processing large datasets.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11615069B2Data filtering using a plurality of hardware accelerators
Publication Date: 2023.03.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11615069B2 patent drawing
  • US11615069B2 patent drawing
  • US11615069B2 patent drawing

AI summary

Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.