Hardware Accelerator for Data Transmission System
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Solution Overview
Problem
Conventional data transmission systems experience increased processor computation loading and reduced data accessing speed due to processor-executed program codes, leading to inefficient data access.
Innovation Solution
A hardware accelerator is introduced in the data transmission system, comprising a decoding unit, descriptor updating unit, access control unit, status packet updating unit, and finite state machine, which decodes command packets, updates descriptors, controls data transfer, and generates status packets to manage data transmission between bus and storage device controllers, thereby reducing processor computation loading and enhancing data accessing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor executes firmware program to access data, then the data transmission system can function properly, but the computation loading of the processor increases and data accessing speed decreases
Solution Approach 1:
A hardware accelerator is introduced as an intermediary component between the processor and storage device controller. The hardware accelerator includes a decoding unit, descriptor updating unit, access control unit, status packet updating unit, and finite state machine that work together to handle data transmission tasks, freeing the processor from executing firmware programs for data access operations.
Solution Approach 2:
The patent replaces the software-based firmware execution mechanism with a hardware-based accelerator. Instead of using the processor to execute firmware programs (software/mechanical system), the system uses dedicated hardware circuits (hardware accelerator) to perform data transmission control functions, thereby improving data accessing speed while maintaining reliability.
2Adaptability or versatility
If the processor executes firmware program to manage data transmission, then comprehensive control is achieved, but the processor computation loading increases
Solution Approach 1:
The patent extracts the data transmission control functionality from the processor by implementing a dedicated hardware accelerator. The hardware accelerator contains specialized units (decoding unit, descriptor updating unit, access control unit, status packet updating unit) that handle specific control tasks, removing the computational burden from the processor while preserving comprehensive control capability.
Solution Approach 2:
The hardware accelerator is segmented into multiple functional units, each responsible for a specific aspect of data transmission control. The decoding unit handles command decoding, the descriptor updating unit manages descriptors, the access control unit controls data access, and the status packet updating unit manages status packets. This segmentation allows comprehensive control functionality to be distributed across specialized hardware components, reducing processor loading.
Data Source
AI summary
A data transmission system for enabling data to be transmitted from one of a host and a storage device to the other includes a bus controller, a command register, a data register, a storage device controller and a hardware accelerator. The bus controller receives a command packet from the host through a bus. The command register and the data register respectively store the command packet and the data received by the bus controller. The storage device controller controls an accessing action of the storage device. The hardware accelerator generates a control command according to the command packet and drives one of the storage device controller and the bus controller to move the data in the data register to the other according to the control command. The hardware accelerator generates a transmission state packet according to a transmission state of the data and outputs the transmission state packet to the host.