Hardware Accelerator for Dictionary Compression Offloading

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current data compression techniques, especially for small payload sizes, suffer from high latency, low throughput, and significant CPU utilization, leading to inefficient data compression and decompression processes.

Innovation Solution

A hardware accelerator is introduced that implements dictionary compression, leveraging its hardware engine to perform the longest possible match in a non-empty history buffer early in the compression process, thereby improving compression ratios and overall data compression performance while offloading CPU workload.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If software-based compression techniques are used, then implementation flexibility is maintained, but processing speed and throughput are reduced

Engineering Contradiction:

Improvecompression speedVSAvoidhardware complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent replaces software-based compression algorithms with dedicated hardware compression circuits that implement the same compression logic in electronic form. The hardware compressor uses circuitry designed specifically for compression operations, substituting the mechanical/software execution model with an electronic hardware model that operates at higher speeds while maintaining the compression algorithm's flexibility through configurable hardware parameters.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If CPU is used for data compression, then general-purpose processing is maintained, but CPU utilization increases and efficiency decreases

Engineering Contradiction:

Improvecompression throughputVSAvoidCPU utilization

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the compression function from the general-purpose CPU by introducing a dedicated hardware compressor module. This segmentation allows the CPU to focus on high-level control and data management tasks while the hardware compressor handles the computationally intensive compression operations independently, thereby reducing CPU utilization and improving overall system productivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The hardware compressor acts as an intermediary component between the CPU and the data to be compressed. It receives compression requests from the CPU, performs the actual compression operations in hardware, and returns the compressed data to the CPU. This intermediary architecture offloads processing work from the CPU, reducing its utilization while increasing compression throughput.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If traditional compression algorithms are used, then compatibility is maintained, but compression ratio and performance are insufficient

Engineering Contradiction:

Improvecompression ratioVSAvoidcompression latency

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The hardware compressor performs preliminary actions by pre-configuring compression parameters and data structures in hardware before actual compression begins. The circuitry is pre-prepared with the necessary logic and state machines to immediately begin compression operations when data is provided, eliminating software initialization overhead and reducing compression latency while achieving improved compression ratios through optimized hardware algorithms.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250110903A1Hardware acceleration of dictionary compression

Publication Date: 2025.04.03 INTEL CORP

AI summary

A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.