Hardware Accelerator Circuit for Near Storage Data Filtering
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Solution Overview
Problem
Current near storage compute systems face challenges in operating at high data rates while reducing data transfer to host devices, due to cost and power constraints, and existing solutions require large, power-hungry CPU cores or numerous DRAM, making them impractical.
Innovation Solution
A hardware accelerator circuit within the memory controller filters data at the drive data rate, reducing the amount of data transferred to the host device by performing search operations locally, using a Column Filter Circuit, Row Filter Circuit, and Data Filter Circuit to process data without repeated data movement between memory and DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If CPU cores are used to perform filtering functions on data from nonvolatile memory, then data can be filtered to reduce transfer amount, but the CPU cores require large size, high cost, and high power consumption
Solution Approach 1:
The patent extracts the filtering function from general-purpose CPU cores and implements it as a dedicated hardware accelerator circuit within the memory controller. This extraction allows the system to achieve filtering capability with lower power consumption and resource requirements, resolving the contradiction between data reduction and power usage.
Solution Approach 2:
The patent replaces the software-based CPU processing mechanism with a hardware-based accelerator circuit. This substitution enables the filtering function to operate more efficiently at the memory controller level, reducing both power consumption and the need for large CPU cores while maintaining data reduction capability.
2Use of energy by moving object
If smaller CPU cores are used to reduce cost and power, then cost and power are reduced, but processing speed becomes slow requiring large additional DRAM
Solution Approach 1:
The patent replaces software-based processing with hardware-based filtering circuits that operate directly in the memory controller. This hardware substitution provides both low power consumption and high processing speed capable of keeping up with the 320 GB/second data rate from 32 SSDs, eliminating the need for additional DRAM.
Solution Approach 2:
The patent segments the filtering function into dedicated hardware circuits (column filter, row filter, data filter) within the memory controller. This segmentation allows each circuit to specialize in specific filtering tasks, achieving high processing speed with minimal power consumption and without requiring additional memory resources.
3Speed
If data is transferred at drive data rate from SSDs, then high data rate is achieved, but host device processors cannot keep up with incoming data
Solution Approach 1:
The patent performs preliminary filtering action at the memory controller level before data reaches the host processor. By pre-filtering data at the source using hardware accelerator circuits, the system maintains high data rate transfer while reducing the volume of data that processors must subsequently handle, enabling processors to keep up with the incoming data stream.
Solution Approach 2:
The patent extracts unnecessary data during the transfer process itself through hardware-based filtering in the memory controller. This extraction occurs at the drive data rate, allowing the system to maintain high throughput while removing data that would otherwise overwhelm host processors.
4Adaptability or versatility
If data is moved back and forth between CPU cores and DRAM for filtering, then filtering function is achieved, but data movement overhead increases
Solution Approach 1:
The patent merges the filtering function directly into the memory controller hardware, combining data access and filtering operations into a single integrated system. This merging eliminates the need for separate data movement between DRAM and CPU cores, reducing data movement overhead and time while maintaining full filtering capability.
Data Source
AI summary
An apparatus is provided that includes a memory system that includes a memory controller coupled to a storage device capable of streaming data at a first data rate. The memory controller is configured to read a first amount of input data from the storage device at an input data rate equals the first data rate, and provide the first amount of input data at the input data rate to a hardware circuit. The hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate. The hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the storage device, a memory buffer, and the hardware circuit.