Hardware Address Conversion Tables for Low-Latency Memory Mapping
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Solution Overview
Problem
Performing logical to physical device address mapping in firmware introduces additional latency to memory systems, which can be a bottleneck in high-performance applications like AI, AR, VR, and gaming, and increases power consumption.
Innovation Solution
Implementing a hardware logic block with address conversion tables, such as a page mapping table and a page type change point table, to perform the conversion of logical page addresses to physical device addresses, reducing latency and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address mapping is performed in firmware, then flexibility and adaptability are maintained, but latency increases and throughput decreases
Solution Approach 1:
The patent segments the address conversion function into two parts: a hardware logic block that performs the actual address conversion operation, and firmware that provides configuration and control. This segmentation allows the time-critical conversion operation to be performed in hardware while maintaining firmware flexibility for configuration.
Solution Approach 2:
The patent introduces a hardware logic block as an intermediary component between the firmware and the address conversion process. This intermediary handles the latency-sensitive conversion operations in hardware while the firmware maintains adaptability through configuration registers and control logic.
2Adaptability or versatility
If address mapping is performed in firmware, then system configurability is preserved, but power consumption increases
Solution Approach 1:
The patent segments the address mapping function into hardware-based execution with firmware-based configuration. This allows power-efficient hardware execution while maintaining configurability through firmware-controlled initialization and parameter setting.
Solution Approach 2:
The hardware logic block is designed to be self-configurable through initialization sequences and control registers, reducing the need for continuous firmware intervention. Once configured, the hardware operates autonomously, reducing overall power consumption while maintaining adaptability.
3Productivity
If hardware logic block with address conversion tables is implemented, then latency is reduced and throughput is improved, but device complexity increases
Solution Approach 1:
The patent uses address conversion tables stored in memory as a simplified representation of the complex mapping relationships. Instead of implementing complex combinatorial logic for all possible address mappings, the system copies relevant mapping data into lookup tables that can be queried efficiently by the hardware logic block.
Solution Approach 2:
The patent makes the address conversion tables configurable through parameters such as table size, entry format, and association with different memory device configurations. This parameter-based configurability allows the same hardware structure to adapt to different complexity requirements without redesigning the entire logic block.
Data Source
AI summary
Methods, systems, and devices for address conversion table supporting hardware automation are described. A memory system may implement a hardware logic block to perform the conversion of a logical page address to a physical device address. The hardware logic block may include a set of one or more tables for address conversion, including a page mapping table, a page type change point table, and a virtual block table, which may support performing the conversion of the logical page address to a physical device address using hardware logic. To account for varying parameters of the memory system, the firmware may load one or more parameters for the hardware logic block, for example, during initialization of the memory system. As such, the hardware logic block may support converting logical page addresses to physical device addresses for various different memory systems and memory system configurations.