Hardware Address Translation Using Low-Order Bits
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Solution Overview
Problem
Current computing environments face inefficiencies in translating input/output addresses to memory addresses, requiring multiple levels of address translation that are resource-intensive and complex, especially when dealing with large memory address spaces and varying page sizes.
Innovation Solution
A computer system and method that utilize a hardware unit to translate input/output addresses by ignoring high-order bits and using only low-order bits to index into address translation tables, reducing the number of translation levels and look-ups, and allowing for flexible address space management and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple levels of address translation are used to translate input/output addresses to memory addresses, then address translation accuracy is improved, but translation complexity and resource consumption increase
Solution Approach 1:
The patent extracts only the necessary low-order bits from the input/output address for translation, ignoring the high-order bits. This selective extraction reduces the translation complexity by focusing only on the relevant address portion while maintaining translation accuracy for the required memory space.
Solution Approach 2:
The address translation process is segmented into two parts: high-order bits are ignored and low-order bits are used for translation. This segmentation allows the system to perform fewer translation look-ups by dividing the address space management into distinct segments with different handling approaches.
2Measurement precision
If multiple levels of address translation look-ups are performed, then address translation accuracy is improved, but translation time increases
Solution Approach 1:
The patent applies partial action by performing translation look-ups using only a portion of the address (low-order bits) rather than the complete address. This reduces the number of translation levels and look-ups required, thereby decreasing translation time while maintaining sufficient accuracy for the address space being managed.
3Reliability
If traditional address translation methods are used, then address space management is maintained, but operating system flexibility is reduced
Solution Approach 1:
The patent introduces dynamic address space management by allowing the operating system to configure which address bits are used for translation and which are ignored. This dynamic approach enables the OS to adapt the translation process to different address space requirements and configurations, enhancing flexibility while maintaining reliable address management.
Data Source
AI summary
An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.