Hardware Model Architecture Search for Power Amplifier Predistortion

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Solution Overview

Problem

Power amplifiers in RF systems face challenges in achieving linearity due to their nonlinear behavior, especially at high power levels, leading to distortion and efficiency trade-offs, and existing digital predistortion techniques struggle with increasing sampling rates and complex signal dynamics.

Innovation Solution

The use of model architecture search techniques, such as differentiable neural architecture search, to optimize the configuration of hardware blocks for digital predistortion, allowing for the discovery of optimal kernel mappings to hardware blocks and improving the accuracy of predistortion models for power amplifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If power amplifiers operate at high power levels, then output power is improved, but linearity deteriorates due to nonlinear behavior

Engineering Contradiction:
Improveoutput powerVSAvoidlinearity
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by using digital predistortion to pre-compensate for the nonlinear behavior of power amplifiers before the signal enters the amplifier. The predistortion model generates corrected signal values that counteract the expected nonlinear distortion, allowing the amplifier to operate at high power levels while maintaining linearity in the final output signal.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If digital predistortion is applied to enhance linearity, then linearity is improved, but device complexity increases

Engineering Contradiction:
ImprovelinearityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by implementing an adaptive predistortion system that dynamically adjusts the predistortion parameters based on feedback from the power amplifier. The system continuously monitors the amplifier's nonlinear behavior and updates the predistortion model accordingly, allowing the complexity to be optimized based on actual operating conditions rather than being fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses feedback mechanisms where the output of the power amplifier is monitored and fed back to the predistortion system. This feedback loop allows the system to learn and adapt to the specific nonlinear characteristics of the amplifier, improving linearity compensation while managing complexity through intelligent adaptation rather than overly complex fixed architecture.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If model architecture search techniques are used to optimize hardware configuration, then manufacturing precision is improved, but loss of time increases due to search and optimization process

Engineering Contradiction:
Improveconfiguration precisionVSAvoidoptimization time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing model architecture search and optimization during the design and manufacturing phase rather than during deployment. The optimal hardware configuration for digital predistortion is determined in advance, allowing the system to achieve high manufacturing precision without incurring time losses during operational phases. The optimized configuration is then implemented directly in the hardware.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20220376659A1Model architecture search and optimization for hardware
Publication Date: 2022.11.24 ANALOG DEVICES INC
  • US20220376659A1 patent drawing
  • US20220376659A1 patent drawing
  • US20220376659A1 patent drawing

AI summary

Systems, devices, and methods related to using model architecture search for hardware configuration are provided. An example apparatus includes an input node to receive an input signal; a pool of processing units to perform one or more arithmetic operations and one or more signal selection operations, wherein each of the processing units in the pool is associated with at least one parameterized model corresponding to a data transformation operation; and a control block to configure, based on a first parameterized model, a first subset of the processing units in the pool, where the first subset of the processing units processes the input signal to generate a first signal.