Hardware-Assisted Shadow Page Table Coherence
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Solution Overview
Problem
Existing virtualization systems face performance degradation and increased latency due to page fault overheads when maintaining coherence between shadow page tables and guest page tables, as they rely on software-initiated mechanisms for intercepting and handling guest writes.
Innovation Solution
The implementation of hardware assistance to provide page table coherence by maintaining a shadow page table in partial correspondence with guest page mappings, marking entries for traced writes, and recording updates in a guest write buffer, allowing the virtualization system to asynchronously update shadow page tables at coherence boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If page protection mechanisms are used to intercept guest writes to maintain shadow page table coherence, then coherence between shadow page tables and guest page tables is ensured, but page fault overheads increase and performance degrades
Solution Approach 1:
The patent replaces the software-based page protection and fault handling mechanism with a hardware-based mechanism. The virtualization hardware automatically tracks guest writes to page table entries and updates shadow page tables without triggering software page faults, thereby eliminating the time loss associated with page fault overhead while maintaining coherence.
Solution Approach 2:
The patent introduces a hardware intermediary (virtualization hardware or MMU extension) that sits between the guest OS and the shadow page tables. This intermediary automatically captures write operations to guest page table entries and propagates them to shadow page tables, eliminating the need for software-mediated page fault handling and reducing time loss.
2Reliability
If software-initiated mechanisms are used to intercept and handle guest writes, then shadow page table coherence is maintained, but device complexity increases due to software intervention overhead
Solution Approach 1:
The patent replaces complex software intervention mechanisms with simplified hardware logic. The virtualization hardware includes dedicated circuits to detect and track writes to page table entries and automatically update shadow page tables, reducing device complexity by eliminating the need for complex software handlers and fault interception mechanisms.
Solution Approach 2:
The patent enables the virtualization hardware to self-manage shadow page table coherence without software intervention. The hardware automatically monitors guest writes, identifies affected shadow page table entries, and performs updates autonomously, thereby reducing device complexity by removing software management overhead.
3Productivity
If hardware assistance is implemented to track memory accesses, then page fault overheads are reduced and performance improves, but device complexity increases due to hardware modifications
Solution Approach 1:
The patent designs the hardware assistance mechanism to serve multiple functions: it tracks guest writes to page table entries, updates shadow page tables, and maintains coherence all within a single integrated hardware component. This multi-functionality improves performance while minimizing device complexity by avoiding separate dedicated hardware for each function.
Solution Approach 2:
The patent merges the shadow page table update function with the existing memory management hardware (MMU or virtualization hardware). By combining these functions into a single hardware unit, the system achieves performance improvement through hardware assistance while minimizing the increase in device complexity through functional integration.
Data Source
AI summary
One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table.