Hardware Bridge for Unified Cache Memory Access

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Solution Overview

Problem

Current Systems-on-Chip (SoC) architectures face inefficiencies in communicating with multiple types of memories, such as Programmable Input/Output (PIO) and Direct Memory Access (DMA) memories, due to the need for constant mode switching and context changes, leading to increased latency and power consumption.

Innovation Solution

A hardware bridge and microcontroller system that translates addressable requests from a Final-Level Cache (FLC) into activation commands for PIO memories, allowing seamless communication across different memory types within a unified address space, reducing the need for explicit mode switching and optimizing data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the system uses separate communication modes for PIO and DMA memories, then each memory type can be accessed with optimized protocols, but the system requires constant mode switching and context changes which increases latency and power consumption

Engineering Contradiction:

Improvememory access efficiencyVSAvoidlatency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent combines PIO and DMA memory interfaces into a unified address space that can be accessed through a single cache hierarchy. The hardware bridge merges the communication paths, allowing the CPU and cache to access both PIO and DMA memories without mode switching, thereby eliminating the time loss associated with context changes while maintaining optimized access paths for each memory type.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The hardware bridge is designed with multi-functionality to handle both PIO and DMA memory access protocols simultaneously. It provides universal access to different memory types through a single interface, eliminating the need for separate communication modes and reducing the latency caused by mode switching while maintaining optimized access for each specific memory type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

Engineering Contradiction:

Improvememory access efficiencyVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent combines PIO and DMA memory interfaces into a unified address space that can be accessed through a single cache hierarchy. The hardware bridge merges the communication paths, allowing the CPU and cache to access both PIO and DMA memories without mode switching, thereby eliminating the power consumption associated with frequent mode changes while maintaining optimized access paths for each memory type.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The hardware bridge is designed with multi-functionality to handle both PIO and DMA memory access protocols simultaneously. It provides universal access to different memory types through a single interface, eliminating the need for separate communication modes and reducing the power consumption caused by mode switching while maintaining optimized access for each specific memory type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Speed

If the system maintains a large DRAM-based system memory, then fast access to processed data is enabled, but significant power is required to maintain data in the volatile memory

Engineering Contradiction:

Improvedata access speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent segments the memory system into a unified address space that includes both volatile and non-volatile memory regions, accessible through a single cache hierarchy. This segmentation allows the system to maintain only the necessary working data in fast DRAM while storing less frequently accessed data in non-volatile memory, reducing the power required to maintain large amounts of data in volatile memory while preserving fast access speeds for active data.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically manages the memory hierarchy, allowing data to be moved between volatile and non-volatile storage based on access patterns. This dynamic approach enables the system to maintain fast access speeds for frequently accessed data in DRAM while minimizing the power consumption associated with maintaining large amounts of data in volatile memory by storing inactive data in non-volatile memory.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10268395B1Systems and methods for communicating addressable requests to a programmable input/output memory over a hardware bridge

Publication Date: 2019.04.23 MARVELL ASIA PTE LTD

AI summary

Systems and methods described herein provide for communicating an addressable request from cache circuitry to a cache memory. The addressable request is received at a hardware bridge coupled to the cache circuitry and is directed to the cache memory, wherein the cache memory includes a direct memory access (DMA) memory and a programmable input/output (PIO) memory operable within a same address space of the cache circuitry. A service command associated with the addressable request is sent from the hardware bridge to a microcontroller. In response to receiving the service command, the microcontroller activates the PIO memory by: 1) transferring write data from an on-die memory to the PIO memory when the service command is a write command, and 2) transferring read data from the PIO memory to the on-die memory when the service command is a read command.