Hardware Compression for BVH Morton Codes and Primitive References

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Solution Overview

Problem

Ray tracing and rasterization techniques in graphics processing are resource-intensive, particularly in real-time applications, due to the computational demands of ray-scene intersection queries and visibility queries in bounding volume hierarchies.

Innovation Solution

Implementing a hybrid approach combining hardware compression for quantized primitive references and Morton code data to optimize ray traversal operations, utilizing a bounding volume hierarchy (BVH) for efficient ray-scene intersection processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional ray tracing is used for real-time rendering, then rendering quality is improved, but computational resource consumption increases significantly

Engineering Contradiction:
Improverendering qualityVSAvoidcomputational resource consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the scene into multiple bounding volume hierarchy (BVH) structures organized in a tree format, allowing ray traversal to be divided into hierarchical levels. This segmentation enables the system to quickly eliminate large portions of the scene that do not intersect with the ray, reducing overall computational requirements while maintaining rendering quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary compression of BVH data using Morton code encoding and quantization before ray tracing operations. By pre-processing and organizing scene data into an optimized structure with reduced memory footprint, the system prepares the data in advance to enable faster traversal and reduce computational overhead during actual ray tracing execution.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If bounding volume hierarchy traversal is performed for ray-scene intersection, then intersection accuracy is improved, but processing time increases

Engineering Contradiction:
Improveintersection accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies quantization to transform floating-point BVH data into lower-precision integer representations, changing the data parameters to reduce memory access time and increase processing speed. This parameter transformation maintains sufficient accuracy for intersection detection while enabling faster computational operations and reduced memory bandwidth requirements.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces Morton code (Z-order curve) encoding to spatially organize BVH nodes, adding a dimensional organization layer that enables cache-friendly memory access patterns. This dimensional reorganization allows the hardware to traverse the BVH structure more efficiently by exploiting spatial locality, reducing memory access latency while maintaining intersection accuracy.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If hardware compression is applied to BVH data, then memory bandwidth is improved, but data structure complexity increases

Engineering Contradiction:
Improvememory bandwidthVSAvoiddata structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces complex software-based BVH traversal and compression algorithms with dedicated hardware circuitry that natively supports Morton code encoding and quantized data processing. This mechanical substitution embeds the compression logic directly in the ray tracing hardware, eliminating the need for complex software data structures and enabling efficient memory bandwidth utilization through specialized hardware pathways.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250308129A1Combination hardware compression for quantized primitive references and morton code data
Publication Date: 2025.10.02 INTEL CORP
  • US20250308129A1 patent drawing
  • US20250308129A1 patent drawing
  • US20250308129A1 patent drawing

AI summary

Apparatus and method for compressing acceleration structure data. For example, one embodiment of a processor comprises: a memory to store an acceleration structure generated based on build data, the build data including primitive reference data structures and Morton code data structures; and circuitry to compress/decompress the build data, the compression/decompression circuitry comprising: de-swizzle/swizzle circuitry to de-swizzle/swizzle Morton code data elements from the Morton code data structures to produce de-swizzled/swizzled Morton code data structures; mapping circuitry to map portions of the de-swizzled/swizzled Morton code data structures and the primitive reference data structures to corresponding compression channels based on types of build data included in the portions; and the corresponding compression channels to generate a corresponding plurality of compressed build data portions to be included in a compression block, or in separate compression blocks for the Morton Code and Primitive Reference data.