Hardware Caching Manager for Transparent Memory Pool Data Movement
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Solution Overview
Problem
Existing data processing systems face challenges in managing data movement between different types of memory technologies, such as slow, high-density Storage Class Memory (SCM) and fast, volatile DRAM, as existing solutions require software intervention and do not efficiently utilize the desirable properties of each memory type.
Innovation Solution
The implementation of a caching manager in hardware, which interacts with the translation lookaside buffer (TLB) and shadow-address table to automatically manage data movement between memory pools, allowing data to be transparently transferred between SCM and DRAM without OS intervention, utilizing access frequency counters and flags to determine page eligibility for caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in high-density SCM memory, then storage capacity is improved, but access speed deteriorates
Solution Approach 1:
The memory system is segmented into multiple pools with different characteristics (SCM pool for high-density storage, DRAM pool for fast access). The caching manager divides memory management into autonomous hardware-controlled operations, separating the functions of storage and caching to resolve the speed-capacity tradeoff.
Solution Approach 2:
A hardware caching manager acts as an intermediary between the SCM and DRAM pools, automatically managing data movement based on access patterns. This intermediary transparently handles data transfer, allowing fast access to frequently used data while maintaining high-density storage in SCM.
2Productivity
If hardware caching manager is implemented, then data movement efficiency is improved, but device complexity increases
Solution Approach 1:
The caching manager operates autonomously using hardware-based access frequency counters and caching flags to automatically determine which data should be cached. This self-service mechanism eliminates the need for software intervention and reduces overall system complexity despite adding hardware components.
Solution Approach 2:
The caching manager performs multiple functions including tracking access patterns, managing data movement between pools, and maintaining caching flags, all within a single hardware component. This multi-functionality improves productivity while controlling the increase in device complexity.
3Ease of operation
If automatic hardware management is used, then software intervention overhead is reduced, but hardware complexity increases
Solution Approach 1:
The hardware caching manager autonomously manages data movement between memory pools using access frequency counters and caching flags, completely eliminating the need for software intervention. This self-service approach reduces software overhead while the hardware complexity is managed through integrated design.
Solution Approach 2:
The patent replaces the mechanical/software-based memory management system with a hardware-based automatic management system. This substitution eliminates software overhead and provides more efficient data movement, with the hardware complexity offset by the elimination of software management layers.
Data Source
AI summary
A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.