Hardware Calculator Register Sharing for Faster Convolution MAC
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Solution Overview
Problem
Conventional hardware computers for calculating convolution products face inefficiencies due to increased inference time as the dimension N increases, primarily limited by the number of input data loading processes, which becomes a bottleneck in the calculation process.
Innovation Solution
An integrated circuit with a hardware calculator that employs two parallel computation paths, each accessing three input registers, allowing four multiplication-accumulation operations with only two data loads per operation by sharing and distributing register access across channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of parallel MAC-type computers is increased to optimize the number of successive instructions, then the calculation speed of convolution product is improved, but the number of input data loading processes increases, making loading samples and taps from memory the limiting factor in terms of time
Solution Approach 1:
The patent merges the functionality of multiple registers into a shared register structure. Specifically, a single register file is designed to serve multiple MAC units simultaneously, allowing them to share the same storage resource. This eliminates the need for separate registers for each MAC unit, thereby reducing the total number of register load operations while maintaining parallel calculation capabilities.
Solution Approach 2:
The shared register structure is designed to be universal, serving multiple MAC units with different calculation requirements. The register file can be accessed by any MAC unit that needs the stored data, making it a multi-functional resource that supports various parallel operations without requiring dedicated storage for each operation.
2Adaptability or versatility
If the dimension N is increased to optimize convolution product applications, then the calculation capability is improved, but the inference time increases quadratically
Solution Approach 1:
The patent segments the calculation work by organizing multiple MAC units to operate in parallel on different portions of the convolution calculation. Each MAC unit handles specific multiplication-accumulation operations simultaneously, dividing the overall computational task into parallel segments that can be executed concurrently, thus reducing the quadratic time complexity associated with increased dimension N.
Data Source
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AI summary
The integrated circuit includes a hardware calculator adapted to calculate, in a series of operations, output components Yn-1 Yn such that: Ym=∑k=0N−1bkxm−k. One operation includes: - in a first calculation channel (VC1), a multiplication-accumulation between first factors {xi, xi-1} contained in a first register (R3) and second factors {bj, bj+1} contained in a second register (R7); - in a second calculation channel (VC2), a multiplication-accumulation between the same first factors {xi, xi-1} and second factors {bj+1, bj+2} contained in the second register (R7) and in a third register (R6); - a loading into the first register (R3) of the first factors {xi-2, xi-3} of the next operation of the two paths, - a loading into the second register (R7) of the second factors {bj+4, bj+5} corresponding to the calculation of the operation following the next operation of the first path (VC1).