Hardware Capability Generation Circuitry for Memory Access Control
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Solution Overview
Problem
In capability-based architectures, the use of compiler-generated capabilities for memory access control leads to increased code size due to the larger size of capabilities and alignment requirements, which is undesirable in memory-constrained systems.
Innovation Solution
The approach involves generating capabilities using processing circuitry that retrieves a literal value from a literal pool and selects constraining information from a limited set of options based on a capability generating instruction, reducing the need for compiler-generated capabilities and minimizing code size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compiler-generated capabilities are used for memory access control, then capability control and security are improved, but code size increases significantly
Solution Approach 1:
The patent extracts the capability generation function from the compiler and relocates it to hardware circuitry. The capability generation circuitry generates capabilities at runtime based on capability generating instructions, eliminating the need for compiler-generated capabilities stored in literal pools. This extraction resolves the contradiction by maintaining secure capability control while significantly reducing code size, as capabilities are generated on-demand rather than being pre-generated and stored.
Solution Approach 2:
The patent replaces the software-based compiler mechanism with a hardware-based capability generation system. Instead of relying on compiler-generated capabilities, the system uses capability generation circuitry that executes capability generating instructions to create capabilities dynamically. This substitution resolves the technical contradiction by providing the same security functionality through a different mechanism that does not require large amounts of stored capability data.
2Reliability
If capabilities are stored in literal pools, then capability generation control is improved, but alignment requirements increase code size
Solution Approach 1:
The patent removes capabilities from the literal pool storage mechanism entirely. Instead of storing capabilities in the literal pool with their alignment requirements, the system uses capability generation circuitry to create capabilities dynamically from capability generating instructions. This eliminates the alignment requirements that would otherwise increase code size, while maintaining control over capability generation through the instruction-based approach.
3Reliability
If compiler generates capabilities at compile time, then capability control is improved, but code size and memory usage increase
Solution Approach 1:
The patent transforms the static capability generation approach into a dynamic one. Instead of generating capabilities at compile time and storing them permanently in literal pools, the system generates capabilities at runtime on-demand based on capability generating instructions executed during program operation. This dynamic approach reduces memory usage significantly, as capabilities are created only when needed and can be discarded afterward, rather than occupying permanent storage space.
Solution Approach 2:
The patent extracts the capability generation function from the compile-time process and implements it as a runtime hardware function. The capability generation circuitry operates during program execution, generating capabilities dynamically rather than pre-generating them during compilation. This extraction resolves the memory usage contradiction by eliminating the need for large literal pools to store pre-generated capabilities.
Data Source
AI summary
A technique is provided for constraining access to memory using capabilities. An apparatus is provided that has processing circuitry for performing operations during which access request to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that provide a pointer value and associated constraining information. The apparatus also provides capability generation circuitry, that is responsive to the processing circuitry executing a capability generating instruction that identifies a location in a literal pool of the memory, to retrieve a literal value from the location in the literal pool, and to produce a generated capability in which the pointer value of the generated capability is determined from the literal value. The constraining information of the generated capability is selected from a limited set of options in dependence on information specified by the capability generating instruction. It has been found that such an approach provides a robust mechanism for generating capabilities, whilst reducing code size.