Hardware Clock Synchronization for Low-Jitter Software Periods
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Solution Overview
Problem
Existing methods for synchronizing clock signals between different computer units result in asynchronous execution of software, leading to jitter and impaired response times, especially in real-time applications, and require protocol-based synchronization that increases computational effort and reduces accuracy.
Innovation Solution
A device and method using a microcontroller with a measurement timer module, input and output units, and a comparison unit to adjust the clock signal based on timer value comparisons, allowing for precise synchronization of software periods without protocol-based synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If protocol-based synchronization (NTP, PTP) is used to synchronize clock signals between different computer units, then time synchronization is achieved, but computational effort increases and transmission time via bus limits achievable accuracy
Solution Approach 1:
The patent extracts the synchronization function from protocol-based software processing and implements it directly in hardware. The measurement timer module and comparison unit operate independently of the main processor, eliminating the need for NTP/PTP protocols and their associated computational overhead while achieving ≤1 μs accuracy through direct hardware timestamp comparison.
Solution Approach 2:
The patent introduces a dedicated hardware intermediary (measurement timer module with register unit) that mediates between the clock signal and the synchronization decision. This intermediary captures timestamps in hardware and provides direct comparison capability, bypassing the bus transmission delays and processing requirements of protocol-based approaches.
2Reliability
If different software programs are executed on independent processors with fixed period, then redundant critical functions are provided, but clock signal tolerances cause time drift and disrupt synchronization
Solution Approach 1:
The patent implements a feedback mechanism where the comparison unit continuously monitors the timestamp difference between processors and the comparison result feeds back to adjust the clock signal period. This closed-loop feedback compensates for clock drift caused by tolerances while maintaining redundant execution on independent processors, achieving both reliability and synchronization precision.
Solution Approach 2:
The patent makes the clock signal period dynamic by allowing adjustment based on synchronization requirements. The comparison unit detects time drift and the system adjusts the period duration of the clock signal accordingly, enabling the system to adapt to clock tolerances and maintain synchronization despite variations in processor clock frequencies.
3Productivity
If asynchronous execution is used to run software on multiple controllers, then computational load is distributed, but jitter increases by the period duration and response time to external events is impaired
Solution Approach 1:
The patent merges the timekeeping and synchronization functions into a unified hardware mechanism that operates across all controllers. The measurement timer module and comparison unit create a shared reference framework that coordinates distributed execution, reducing jitter by ensuring that timestamp comparisons and synchronization decisions are made with consistent timing across all processors.
Data Source
AI summary
A device for synchronising a clock signal for a software comprises a processor for executing the software based on the clock signal, a measurement timer module that increments a timer value based on a device clock, an output unit designed to output a signal at the start of a synchronisation period defined by the software period or a multiple thereof, an input unit, a register unit designed to store a current timer value of the measurement timer module at the end of a synchronisation period, and a comparison unit designed to compare the timer value stored in the register unit with the synchronisation period, and, depending on a comparison result, to adjust at least one subsequent period duration of the clock signal for the software executed on the processor. The measurement timer module is designed to reset the timer value to a start value when an input signal is received.