Hardware Code Path Verification for Microprocessor Execution
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Solution Overview
Problem
Existing microprocessor-based systems face limitations in verifying correct program execution due to low checkpoint granularity and limited reliability, as they rely on self-verification methods that do not continuously monitor program execution, making them vulnerable to errors and malicious attacks.
Innovation Solution
A hardware code path verifying stage with a continuous error detection code generator is implemented, which continuously calculates error detection codes during program execution and compares them with predetermined values at specific breakpoints, providing high granularity and safety without additional data processing time, using methods like cyclic redundancy checks, parity bits, checksums, and Hamming distance checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If checkpoints are inserted into the program code for verification, then program execution correctness can be detected, but the granularity of verification is limited and execution time increases
Solution Approach 1:
The patent replaces the mechanical approach of inserting software checkpoints into the program code with a hardware-based error detection code generator that continuously verifies program execution. The hardware EDC generator operates independently from the microprocessor, performing verification operations in parallel without interfering with the normal execution flow, thus achieving continuous verification without time loss.
Solution Approach 2:
The patent introduces a hardware intermediary component (EDC generator and comparison logic) that sits between the program execution and the verification process. This intermediary continuously generates error detection codes from the executing program and compares them against expected values, enabling verification without requiring the microprocessor to pause or insert checkpoints in the original code.
2Reliability
If self-verification methods are used in the program code, then verification can be performed, but reliability is limited due to lack of independent monitoring
Solution Approach 1:
The patent segments the verification function from the execution function by implementing a separate hardware EDC generator that operates independently from the microprocessor. This segmentation creates an independent monitoring path that does not rely on the correctness of the executing program, thereby improving reliability while maintaining manageable complexity through functional separation.
Solution Approach 2:
The hardware EDC generator acts as an independent intermediary that monitors program execution without being part of the executed code itself. This independent intermediary generates verification data through a separate computational path, ensuring that the verification process is not compromised by errors in the program being verified.
3Reliability
If continuous verification is implemented, then highest granularity and safety standards are achieved, but additional data processing time is required
Solution Approach 1:
The patent replaces the software-based verification mechanism with a hardware implementation of the EDC generator. This hardware implementation performs continuous error detection code generation and comparison operations in parallel with program execution, eliminating the need for the microprocessor to allocate additional processing time for verification and maintaining full data processing throughput.
Solution Approach 2:
The patent merges the verification operations with the execution operations by implementing both simultaneously in hardware. The EDC generator operates concurrently with the microprocessor execution, combining the useful action of program execution with the verification action of continuous EDC generation and comparison, thereby achieving continuous verification without sacrificing productivity.
Data Source
AI summary
An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.