Hardware Coherency Manager for Multi-Processor Data Sharing

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Solution Overview

Problem

The existing PCI bus relies heavily on device driver software to maintain workload coherency between multiple processing devices, leading to complex software management and reduced system performance due to the burden of coherency and traffic management.

Innovation Solution

Implementing hardware blocks within processing devices to track and manage both coherent and non-coherent data, using hardware-implemented blocks to coordinate and synchronize data sharing between processing devices, thereby offloading the software burden and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If device driver software is used to maintain workload coherency between multiple processing devices, then coherency can be maintained, but software complexity increases and system performance decreases

Engineering Contradiction:

Improveworkload coherencyVSAvoidsoftware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces software-based coherency management with hardware-based coherency management. A hardware coherency manager is introduced that operates at the hardware level to track and manage workload coherency between processing devices, eliminating the need for complex device driver software and reducing software complexity while maintaining coherency reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware coherency manager acts as an intermediary between multiple processing devices and the PCI bus. It centralizes coherency management functions, coordinating data transfers and workload distribution at the hardware level, thereby simplifying the software layer while ensuring reliable coherency maintenance across devices.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If device driver software manages traffic between multiple processing devices, then traffic can be coordinated, but system performance is reduced due to software processing overhead

Engineering Contradiction:

Improvetraffic coordinationVSAvoidsystem performance

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent substitutes software-based traffic management with hardware-based traffic management. The hardware coherency manager handles traffic coordination, data routing, and workload distribution at the hardware level, eliminating software processing overhead and improving system performance while maintaining ease of traffic coordination.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware coherency manager enables self-service traffic management by automatically tracking data coherence states and coordinating transfers between processing devices without software intervention. This autonomous hardware-level management improves system performance by eliminating software processing bottlenecks while maintaining proper traffic coordination.

Inventive Principle:

Principle #25Self-service

3Reliability

If software is used for coherency management, then coherency can be maintained, but the burden on software increases leading to lower performance

Engineering Contradiction:

Improvecoherency maintenanceVSAvoidsoftware processing burden

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based coherency management with hardware-based coherency management. The hardware coherency manager performs coherency tracking, data validation, and coordination functions at the hardware level, eliminating the processing burden on software while maintaining reliable coherency maintenance across multiple processing devices.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9626316B2Managing shared resources between multiple processing devices

Publication Date: 2017.04.18 INTEL CORP

AI summary

In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.