Hardware Comparator for Redundant Multi-Threading Error Detection
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Solution Overview
Problem
In redundant multi-threading operations, verifying the correctness of computation results across multiple threads in a SIMD architecture is complex and cumbersome for programmers, as it requires explicit instructions to force threads to run redundantly and compare values, complicating error detection and handling.
Innovation Solution
The introduction of a hardware-assisted RMT compare instruction that allows work-items to transmit values and addresses for comparison to a hardware comparator unit, which performs error actions such as returning error codes or triggering fault handling if mismatches are detected, simplifying the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If explicit instructions are used to force threads to run redundantly and compare values, then error detection capability is improved, but program complexity increases
Solution Approach 1:
The system performs redundant multi-threading operations automatically without requiring explicit programmer instructions. The compute unit executes the same operation multiple times with different threading configurations and self-computes hash values to detect errors, eliminating the need for complex explicit comparison instructions while maintaining error detection capability
Solution Approach 2:
A hash computation mechanism is introduced as an intermediary to simplify error detection. Instead of requiring explicit value comparisons between multiple thread executions, the system computes hash values of the results and compares these simplified representations, reducing program complexity while preserving error detection functionality
2Measurement precision
If explicit value comparison instructions are implemented, then computation correctness verification is improved, but instruction complexity increases
Solution Approach 1:
The system extracts the essential verification information by computing hash values from the full computation results. This extraction process simplifies the comparison operation while maintaining the ability to detect computation errors, reducing instruction complexity without sacrificing verification precision
Solution Approach 2:
The system transforms the verification problem by changing from direct value comparison to hash value comparison. This parameter transformation simplifies the comparison operation while preserving error detection capability, reducing instruction complexity while maintaining measurement precision
Data Source
AI summary
Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action.