Hardware Control-Flow Validation Using Quasi NOP Identifiers
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Solution Overview
Problem
Existing systems face challenges in efficiently validating control-flow transfers to prevent exploitation of software flaws by malicious attackers, as current defensive mechanisms are not effective in all cases and require complex obfuscation methods that impact performance.
Innovation Solution
A method and apparatus for control-flow validation using a new quasi NOP instruction with 'free' bits that can be set without altering the instruction's behavior, generating identifiers for source and target packets through computations, and comparing these identifiers to detect invalid control flows, thereby preventing unauthorized execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption or obfuscation is used to protect control flow, then security against attackers is improved, but verification of the decrypted value becomes very hard and performance degrades
Solution Approach 1:
The patent extracts the verification function from complex encryption/obfuscation schemes and implements it directly in hardware circuitry. The control flow validation logic is taken out of the software domain and embedded as dedicated hardware components that automatically verify control flow integrity without requiring complex software-based decryption and verification processes.
Solution Approach 2:
The patent introduces an intermediary hardware validation mechanism that sits between the control flow execution units and the program counter. This intermediary hardware component performs automated validation of control flow transfers, acting as a mediator that simplifies the verification process compared to direct software-based encryption verification.
2Reliability
If complex obfuscation methods are used to prevent exploitation, then security is improved, but performance degradation occurs
Solution Approach 1:
The patent replaces software-based obfuscation and verification mechanisms with hardware-based control flow validation circuitry. By substituting the mechanical/software execution of complex obfuscation algorithms with dedicated hardware validation logic, the system achieves both security and performance, as hardware operations execute faster and more efficiently than software equivalents.
3Reliability
If general defensive features are used to mitigate exploits, then protection against well-known techniques is improved, but effectiveness against all cases is limited
Solution Approach 1:
The patent implements a universal control flow validation mechanism that provides multi-functional protection. The hardware validation circuitry can detect and prevent multiple types of control flow exploits including return-oriented programming, jump-oriented programming, and other advanced persistent threats, making the defense system versatile against various attack vectors rather than limited to specific exploit types.
Data Source
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AI summary
Disclosed are methods and apparatus for packet based validation of control flow transfers for hardware control-flow enforcement. The methods and apparatus achieve control-flow validation through the determination of a first identifier for a source packet that implements a jump, where the determination is based on a computation using contents within the source packet itself. Similarly, a second identifier is determined for a target packet to which the source packet is directed based on a computation using contents of the target packet. The identifiers may be predetermined based on the packet contents, and may also involve insertion of No Operation instructions to ensure the computations based on the packet contents yield the desired identifiers. The identifiers may then be compared to determine whether they match or are compatible, and an invalid control flow can be detected if they are not compatible.