Hardware Co-Simulation Interface for Embedded System Profiling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current profiling techniques for hardware/software embedded systems are inefficient due to intrusive methods, limited precision, and resource scarcity, making it difficult to effectively measure performance and identify bottlenecks in hardware-software partitioning.
Innovation Solution
A hardware co-simulation interface is generated between a programmable logic device (PLD) and a computer, using shared FIFO logic to store and transmit profiling data, allowing for non-intrusive, real-time detection and analysis of events, and preventing data loss by monitoring and managing on-chip memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cycle-accurate software simulation is used for profiling, then measurement precision is improved, but productivity deteriorates due to large amount of computation required
Solution Approach 1:
The patent extracts the profiling function from the main software simulation by implementing dedicated hardware profiling logic in the PLD. This separate profiling mechanism monitors events and stores data in on-chip memory without requiring full cycle-accurate software simulation, thus achieving precise profiling measurements while significantly improving productivity by reducing computation requirements.
Solution Approach 2:
The patent introduces an intermediary hardware profiling logic layer between the PLD and computer. This intermediary component captures profiling events and stores them in on-chip memory, acting as a mediator that enables precise measurement without requiring continuous complex software simulation. The intermediary handles the profiling tasks independently, improving overall system efficiency.
2Measurement precision
If intrusive profiling code is inserted into software program, then measurement precision is improved, but device complexity increases and reliability deteriorates due to changed cycle-by-cycle behavior
Solution Approach 1:
The patent extracts the profiling functionality from the software program by implementing dedicated hardware profiling logic in the PLD. This separates the profiling function from the main software execution, eliminating the need to insert intrusive code into the software program. The hardware-based approach maintains the original software cycle-by-cycle behavior while achieving precise profiling measurements.
Solution Approach 2:
The patent replaces the software-based intrusive profiling mechanism with a hardware-based profiling system. Instead of using software interrupts and service routines, the hardware profiling logic directly monitors events and captures data in on-chip memory. This substitution eliminates the complexity and behavioral changes associated with software interrupts while maintaining measurement precision.
3Measurement precision
If on-chip PLD resources are used to store profiling data, then measurement precision is improved, but device complexity increases due to competition for scarce PLD resources
Solution Approach 1:
The patent extracts the profiling data storage function from the general PLD resources by dedicating specific on-chip memory blocks to profiling purposes. This separation ensures that profiling data storage does not compete with other PLD resources for the same memory space, eliminating resource competition complexity while maintaining precise profiling data storage capacity.
Solution Approach 2:
The patent applies local quality by assigning dedicated on-chip memory resources specifically for profiling data storage. Instead of using general-purpose PLD resources that may be needed for other functions, the patent designates specific memory regions exclusively for profiling, ensuring sufficient storage capacity without creating resource conflicts or management complexity.
4Productivity
If hardware co-simulation interface is implemented with shared FIFO logic, then productivity is improved through real-time profiling, but device complexity increases
Solution Approach 1:
The patent implements universality by designing the shared FIFO logic to serve multiple functions: it acts as both a buffer for profiling data transfer between PLD and computer, and as a synchronization mechanism for real-time profiling. This multi-functional design enables real-time profiling capability while minimizing the overall complexity by reducing the number of separate components needed.
Data Source
AI summary
Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of events. The embedded system in the PLD is simulated. During the simulation of the embedded system, occurrence of at least one event is detected to produce profiling data. The profiling data is stored into shared first-in-first-out (FIFO) logic of the PLD and the computer. The profiling data is retrieved from the shared FIFO logic at the computer.