Hardware-Based CPU Reset Detection Circuit
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Solution Overview
Problem
Existing factory reset capabilities rely on software and GPIO pins, which are unreliable and dependent on host software, making them prone to crashes and limiting the range of reset levels and availability.
Innovation Solution
A hardware-based detection mechanism that uses a counter circuit to count clock cycles when a CPU reset request is asserted, allowing the CPU to perform a factory reset based on the duration of the request, independent of CPU operation and host software, thereby reducing GPIO requirements and ensuring a standard reset capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based factory reset capability is used with GPIO pins, then the device can perform factory reset operations, but the system becomes dependent on host software and GPIO resources, reducing reliability during software crashes
Solution Approach 1:
The patent replaces the software-based GPIO polling mechanism with a hardware-based detection circuit that directly monitors the reset button state. The hardware circuit independently detects button presses and generates reset signals without requiring host software intervention, thereby eliminating software dependency and improving reliability during software crashes.
Solution Approach 2:
The patent introduces a hardware intermediary circuit between the reset button and the CPU that processes reset requests independently. This intermediary hardware layer filters and conditions reset signals, providing a reliable interface that does not depend on host software availability or GPIO resource allocation.
2Ease of operation
If GPIO pins are used for reset detection, then reset functionality is available, but GPIO resources are consumed and interrupt monitoring requires host software support
Solution Approach 1:
The patent extracts the reset detection functionality from the general-purpose GPIO system and implements it as a dedicated hardware circuit. This separate detection circuit directly monitors the reset button and generates appropriate signals without consuming GPIO resources or requiring interrupt monitoring, thereby freeing GPIO pins for other uses.
Solution Approach 2:
The hardware-based detection circuit provides universal reset functionality that operates independently of the GPIO subsystem. By creating a dedicated detection path, the system ensures reset capability is always available regardless of GPIO configuration or software state, making the reset function universally accessible.
3Reliability
If hardware circuit is used to count clock cycles for reset duration, then reset detection is independent of CPU operation, but additional hardware components are required
Solution Approach 1:
The patent merges the clock cycle counting function with the existing hardware reset detection circuit. The same hardware that detects reset button presses also counts clock cycles during the button press duration, eliminating the need for separate counting hardware and reducing overall circuit complexity while maintaining independent operation.
Data Source
AI summary
A hardware based detection approach for detecting a CPU reset request and a CPU boot process that resets control parameters that control operation of the CPU are described. Described embodiments of the hardware based detection approach store a count of clock cycles that elapse while a CPU reset request switch is actuated. As part of the reset process, the CPU retrieves the stored clock cycle count and based on the value of the retrieved clock cycle count, i.e., based on the duration that the CPU reset switch was physically actuated, the CPU boot process resets one or more sets of CPU control parameters to original factory settings.