Hardware Data Merge Unit for Interleaved Network Stream Analysis

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Solution Overview

Problem

Conventional network analyzers face challenges in merging data from multiple channels into a single interleaved data stream at high network bandwidth rates, leading to data frame loss and high CPU utilization due to software-based merge functions, which require significant memory and processing resources.

Innovation Solution

A data merge unit is implemented in hardware, such as ASICs or FPGAs, that receives and arranges complete data frames from multiple channels into an interleaved data stream without software post-processing, enabling full line rate merging and reducing system bandwidth and CPU usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based merge function is used to merge data from multiple channels, then the system can process network data, but the CPU utilization increases significantly and data frame loss occurs at high bandwidth rates

Engineering Contradiction:

Improvedata processing rateVSAvoidCPU utilization

Core Design Contradiction:

ProductivityVSExtent of automation

Solution Approach 1:

The patent replaces the software-based merge function with a hardware-based merge unit implemented in ASICs or FPGAs. This substitution moves the data merging operation from the CPU to dedicated hardware circuitry, enabling parallel processing and eliminating the bottleneck where software-based merging caused high CPU utilization and data frame loss at high bandwidth rates.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If software-based merge function is used to merge data from multiple channels, then the system can process network data, but the memory requirements increase significantly

Engineering Contradiction:

Improvedata processing rateVSAvoidmemory requirements

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If time stamps are added to each frame for merging, then the data can be correctly ordered, but the system bandwidth and memory requirements increase

Engineering Contradiction:

Improvetime stamp accuracyVSAvoidsystem bandwidth

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent applies time stamps in hardware as data frames are received and tagged with time stamps in a descriptor field before the merging process. This preliminary action ensures time stamp accuracy is maintained while the hardware merge unit processes the tagged frames, avoiding the need for additional software processing that would increase bandwidth and memory requirements.

Inventive Principle:

Principle #10Preliminary action

4Adaptability or versatility

If hardware resources are replicated for each input channel, then each channel can be processed independently, but the device complexity and cost increase

Engineering Contradiction:

Improvechannel processing capabilityVSAvoidhardware resource replication

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple input channels into a single interleaved data stream using a hardware merge unit. Instead of replicating hardware resources for each channel, the design combines channel processing functions into a unified hardware structure that handles multiple channels simultaneously, reducing device complexity and cost while maintaining the ability to process data from multiple channels independently.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7711006B2Data merge unit, a method of producing an interleaved data stream, a network analyser and a method of analysing a network

Publication Date: 2010.05.04 NAPATECH

AI summary

A data merge unit is provided for providing an interleaved data stream, the data stream including data frames received on two or more input channels, wherein data frames from each of the two or more input channels are arranged in time-slots of the interleaved data stream. The data merge unit comprises an input unit to receive data frames from two or more input channels, a frame merge buffer arranged to receive data frames from the two or more input channels via the input unit and store said data frames; and, an output generator to generate the interleaved data stream, the output generator being configured to select complete data frames from the frame merge buffer and arrange said complete data frames in the interleaved data stream.