Hardware Debugging Apparatus for Software Pipelined Programs

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Solution Overview

Problem

Software pipelining complicates hardware debugging by causing premature execution of code sections during trigger events, leading to inconsistencies between variable values in software-pipelined programs and their source counterparts.

Innovation Solution

A hardware debugging apparatus and method that sets a trigger iteration count value based on iteration count and execution block differences, generating predicates in advance to manage processor restarts and backup register/memory values, ensuring correct execution block processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software pipelining is used to improve processing performance, then processing performance is improved, but debugging difficulty increases

Engineering Contradiction:

Improveprocessing performanceVSAvoiddebugging difficulty

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by generating predicates in advance for execution blocks before the actual execution occurs. The predicate generation happens during compilation or before runtime, allowing the debugging system to pre-calculate which execution blocks should be executed in each iteration. This preliminary preparation eliminates the need to recalculate execution semantics during debugging, thereby resolving the contradiction between maintaining software pipelining performance and enabling accurate debugging.

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If trigger events are used to stop processor execution for debugging, then debugging capability is improved, but execution consistency deteriorates

Engineering Contradiction:

Improvedebugging capabilityVSAvoidexecution consistency

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent implements feedback by continuously monitoring the iteration count and comparing it against predetermined thresholds during processor execution. When a trigger event occurs, the system uses the feedback from the current iteration count to determine whether to stop execution or allow it to continue. This feedback mechanism ensures that stopping the processor at appropriate points maintains execution consistency, as the decision to stop is based on real-time iteration information rather than arbitrary halting.

Inventive Principle:

Principle #23Feedback

3Productivity

If multiple iterations are overlapped to improve throughput, then throughput is improved, but variable value accuracy deteriorates

Engineering Contradiction:

ImprovethroughputVSAvoidvariable value accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies segmentation by dividing the software-pipelined program into distinct execution blocks with associated predicates for each block. Each execution block is assigned a predicate that determines its execution status in each iteration. This segmentation allows the system to maintain multiple overlapping iterations while ensuring that each execution block is executed with the correct predicate value, thereby preserving variable value accuracy even as throughput increases through iteration overlap.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9542188B2Hardware debugging apparatus and method for software pipelined program

Publication Date: 2017.01.10 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.