Hardware Design Verification Using Constant Kth Difference
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Solution Overview
Problem
Existing methods for formally verifying hardware designs that implement functions polynomial in one or more input variables face challenges in converging results, particularly when dealing with large input domains or complex functions, as they struggle to present mathematical problems effectively for formal verification tools.
Innovation Solution
The proposed solution involves verifying that an instantiation of the hardware design has a constant kth difference for a sub-function p over a set of values, which allows for formal verification of the hardware design's polynomial nature and expected output generation for specific values, using methods that include identifying and comparing outputs for consecutive input values and employing formal verification tools to establish assertions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on hardware designs implementing polynomial functions over large input domains, then verification completeness is improved, but verification time and computational resources increase exponentially
Solution Approach 1:
The verification process is segmented into two distinct phases: (1) formal verification of the constant kth difference property over the entire input domain, and (2) spot checking of expected outputs at k+1 specific input values. This segmentation allows the complex verification task to be divided into manageable parts, where the formal verification establishes a general property that applies to all inputs, and spot checking validates specific cases, thereby reducing overall verification time while maintaining completeness.
Solution Approach 2:
The method performs preliminary formal verification of the constant kth difference property before performing spot checking of expected outputs. This preliminary action establishes a mathematical guarantee that the hardware design implements a polynomial function of degree at most k-1, which then simplifies the subsequent spot checking process. By performing this preliminary formal verification, the method reduces the state space that needs to be explored during spot checking, thereby reducing verification time while maintaining reliability.
2Measurement precision
If formal verification tools are used to verify polynomial function implementation, then verification accuracy is improved, but device complexity and verification setup complexity increase
Solution Approach 1:
The method changes the parameter being verified from the full polynomial function output to the constant kth difference property. Instead of verifying that the hardware design computes the correct polynomial output for all inputs, the method verifies that the kth difference of the output is constant for all inputs. This parameter change simplifies the verification setup because it transforms a complex functional verification into a simpler property verification that can be expressed as a mathematical assertion in formal verification tools, thereby reducing setup complexity while maintaining verification accuracy.
3Reliability
If the hardware design is verified to generate expected outputs for all input values, then verification thoroughness is improved, but the number of test cases and verification effort increase
Solution Approach 1:
The method performs partial verification by spot checking expected outputs at only k+1 specific input values rather than all possible input values. This partial action is sufficient because the formal verification of the constant kth difference property already provides a mathematical guarantee that the hardware design implements a polynomial function of degree at most k-1. The spot checking of k+1 values provides additional confirmation and validates the implementation against the mathematical model, achieving thorough verification with improved efficiency by avoiding exhaustive testing of all input combinations.
Data Source
AI summary
Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.