Hardware Design Translation to Logic Code Model
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Solution Overview
Problem
Current hardware design techniques are inefficient due to extensive validation and verification processes and lack of addressing data flow control and protocol logic within existing hardware description languages, leading to increased design schedules and errors.
Innovation Solution
A system and method for translating hardware designs into a graph-based common representation, generating logic code and flow control code for each hardware module node, and storing a logic code model that includes both, facilitating simulation and synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current hardware description languages are used for hardware design, then hardware design can be performed, but validation and verification processes become excessively lengthy and time-consuming
Solution Approach 1:
The patent segments the hardware design into distinct computational kernels and data flow components, allowing independent verification of each segment. This modular approach enables parallel validation processes, reducing overall verification time while maintaining comprehensive coverage of design correctness.
Solution Approach 2:
The patent introduces an intermediate representation layer between hardware description and validation processes. This intermediary enables automated semantic analysis and formal verification methods to operate more efficiently, reducing the time required for comprehensive validation without sacrificing reliability.
2Adaptability or versatility
If current hardware description languages are used, then basic hardware logic can be described, but data flow control and protocol logic are not adequately addressed
Solution Approach 1:
The patent extends the hardware description language to provide universal constructs that handle both traditional logic description and data flow control, as well as protocol logic. These multi-functional primitives allow designers to express complex data flow and protocol behaviors without requiring separate specialized languages or tools.
Solution Approach 2:
The patent implements self-service mechanisms where the extended language automatically generates data flow control structures and protocol validation logic from high-level descriptions. This automation reduces the apparent complexity for designers while providing comprehensive data flow and protocol handling capabilities.
3Reliability
If manual validation and verification processes are used, then design correctness can be checked, but the process becomes tedious and error-prone
Solution Approach 1:
The patent implements automated feedback mechanisms that continuously verify design correctness during the compilation and synthesis processes. The system automatically detects and reports verification failures, providing immediate feedback to designers without requiring manual intervention, thereby maintaining high reliability while reducing operational effort.
Solution Approach 2:
The patent replaces manual mechanical verification processes with automated electronic verification systems. These systems use formal methods and automated theorem proving to check design correctness, eliminating human error and tedium while maintaining or improving verification thoroughness.
Data Source
AI summary
A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware design stored in a hardware model database. Logic code is generated for each hardware module node of the graph-based common representation of the hardware design. Additionally, flow control code is generated for each hardware module node of the graph-based common representation of the hardware design. A logic code model of the hardware design that includes the generated logic code and the generated flow control code is stored.