Hardware Design Verification for Data Transformation Pipelines
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Solution Overview
Problem
Existing formal verification tools struggle to verify the output of hardware designs for data transformation pipelines over infinite time, particularly in ensuring that the pipeline produces correct results regardless of when the transformation is performed, due to their proficiency in either verifying properties related to data transformations or over infinite time, but not both.
Innovation Solution
The method involves generating a version of the hardware design where data transformation elements are replaced with or linked to function elements treated as unevaluated functions by the formal verification tool, allowing for the verification of consistent output production across different transaction states, and using constraints to simplify calculations, thereby increasing the likelihood of formal verification convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing formal verification tools are used to verify data transformation pipelines, then verification of data transformation properties is possible, but verification over infinite time cannot be performed
Solution Approach 1:
The patent introduces an intermediary function element that acts as a mediator between the data transformation element and the verification system. This function element is treated as an unevaluated function by the formal verification tool, allowing the tool to verify properties without needing to evaluate the actual transformation over infinite time. The intermediary absorbs the complexity of the transformation while maintaining verifiable interfaces.
Solution Approach 2:
The patent changes the parameter representation by treating the data transformation element as a function with symbolic parameters rather than concrete evaluations. The function element is defined with input and output parameters that can be verified formally without requiring actual computation over infinite time periods. This parameter transformation enables the verification tool to work within its capabilities.
2Reliability
If data transformation elements are verified for all possible execution states, then functional consistency is ensured, but verification complexity increases
Solution Approach 1:
The patent extracts the complex data transformation element and replaces it with a simpler function element that has the same input-output behavior but is treated as an unevaluated function. This extraction removes the computational complexity from the verification process while preserving the functional properties that need to be verified. The function element can be verified without needing to analyze the internal complexity of the original transformation element.
3Measurement precision
If formal verification is performed without simplifying constraints, then complete verification is attempted, but convergence likelihood decreases
Solution Approach 1:
The patent applies partial verification by focusing on the essential functional properties rather than attempting to verify all possible aspects of the data transformation pipeline. By treating the transformation element as an unevaluated function, the verification process concentrates on input-output consistency and functional equivalence, achieving sufficient verification without the computational burden of complete verification. This partial action approach increases convergence likelihood while maintaining verification effectiveness.
Data Source
AI summary
Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.