Hardware DMA Memory-to-IO Transfer via Dependency Table
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Solution Overview
Problem
Conventional data storage systems require processor intervention for each step of data transfer from memory to IO bus, leading to inefficiencies and increased latency due to the need for multiple DMA engine operations and cache intermediation.
Innovation Solution
The use of a dependency table to facilitate autonomous DMA engine operations and bus snooping to bypass the cache, allowing direct data transfer from memory to the IO bus, thereby reducing processor intervention and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer from memory to IO bus goes through cache with multiple DMA engines, then data transfer can be completed in two steps with parallel buffer operations, but processor intervention is required for each transfer setup increasing latency and reducing efficiency
Solution Approach 1:
The dependency table enables DMA engines to autonomously coordinate their operations without processor intervention. Each DMA engine checks the dependency table to determine when to initiate transfers, allowing the system to self-manage the complex coordination that would otherwise require processor involvement for each transfer setup.
Solution Approach 2:
The dependency table is pre-configured with all transfer dependencies before data transfer begins. This preliminary setup allows DMA engines to autonomously execute the transfer sequence without requiring the processor to prepare each transfer step dynamically, eliminating repeated processor intervention overhead.
2Reliability
If data transfer uses cache as intermediate buffer, then data can be transferred from memory to cache and then to IO bus, but the transfer path is extended increasing latency
Solution Approach 1:
The invention extracts the cache intermediate step from the critical data transfer path. By using the dependency table to directly coordinate memory-to-IO transfers, the system removes the unnecessary cache indirection that increases latency, while maintaining transfer reliability through the deterministic coordination mechanism.
3Adaptability or versatility
If processor prepares each DMA transfer upon interruption, then transfers can be setup dynamically, but precious processor cycles are consumed repeatedly reducing overall system performance
Solution Approach 1:
The dependency table enables the DMA subsystem to self-configure transfers autonomously. Each DMA engine independently checks the dependency table to determine transfer readiness and initiates transfers without processor intervention, eliminating the repeated context switching and setup overhead that consumes processor cycles.
Solution Approach 2:
The dependency table acts as an intermediary data structure that stores transfer coordination information in hardware. This intermediary allows DMA engines to communicate and coordinate their operations without requiring the processor as a mediator, freeing processor cycles for productive work while maintaining transfer flexibility.
Data Source
AI summary
In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.