Hardware EEPROM Reset via Virtual CPU and Frequency Counter
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Solution Overview
Problem
Conventional EEPROMs require CPU intervention for resetting, which can be resource-intensive and inefficient, especially in scenarios like power loss or system resets, and they lack a method for independent electrical erasure without UV light.
Innovation Solution
A hardware-based system that generates a clock signal and data signal to reset an external two-wired EEPROM using a virtual CPU integrated within a finite state machine, allowing for EEPROM resetting without CPU intervention, utilizing a frequency counter to generate a suitable clock signal from a higher frequency source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPU intervention is used for EEPROM resetting, then the resetting can be performed, but CPU resources are consumed and system efficiency is reduced
Solution Approach 1:
The system enables self-service by implementing an autonomous reset mechanism where the microcontroller automatically detects EEPROM reset conditions and generates the necessary reset signals without CPU intervention. The reset controller monitors EEPROM status and independently executes reset sequences, allowing the system to maintain EEPROM reliability while preserving CPU resources for other tasks.
Solution Approach 2:
The resetting function is segmented from the CPU by introducing a dedicated reset controller module. This segmentation separates the EEPROM reset functionality from the main CPU, allowing independent operation of the reset mechanism. The reset controller handles EEPROM reset operations autonomously while the CPU continues executing other program instructions, thus resolving the contradiction between reliable resetting and CPU efficiency.
2Productivity
If hardware-based resetting is implemented, then CPU intervention is eliminated and efficiency is improved, but device complexity increases
Solution Approach 1:
The reset controller is designed as a multi-functional module that handles both EEPROM reset operations and general system reset functions. By making the reset controller universal, the same hardware circuit serves multiple purposes: generating reset signals for EEPROM, managing system reset sequences, and coordinating with the microcontroller. This universality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while maintaining high resetting efficiency.
Solution Approach 2:
The patent merges the reset control functionality with the existing microcontroller architecture by integrating a reset controller that works in conjunction with the microcontroller's existing reset management capabilities. This merging approach allows the hardware-based EEPROM resetting to be implemented within the existing system framework, sharing common control signals and timing mechanisms, thus minimizing the additional complexity introduced by the hardware solution.
3Ease of operation
If conventional EEPROM resetting is used, then the process is simple, but it cannot operate during power loss or system resets
Solution Approach 1:
The system implements preliminary action by detecting reset conditions before they fully occur and initiating the EEPROM reset sequence in advance. The reset controller monitors system status signals and prepares the EEPROM reset before power loss or system reset events complete, ensuring that the EEPROM is properly reset even during adverse conditions. This preliminary detection and preparation mechanism maintains operational simplicity while enabling versatility under power loss or system reset scenarios.
Solution Approach 2:
The reset controller incorporates feedback mechanisms that continuously monitor system status, including power loss conditions and reset signals. When specific feedback indicators indicate a reset condition, the controller automatically activates the EEPROM reset sequence. This feedback-driven approach allows the system to adapt to power loss and system reset events while maintaining a simple operational interface, as the entire process is automatically triggered by system feedback signals.
Data Source
AI summary
Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.