Hardware-Efficient UNORM Rounding With Shift-Add Logic
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Solution Overview
Problem
Existing methods for converting unsigned normalized numbers (UNORM) between different bit lengths in hardware implementations are inefficient in terms of silicon area, processing power, and time due to the use of complex multiplication and division operations, and simple truncation methods introduce significant errors.
Innovation Solution
A binary logic circuit and method for rounding an unsigned normalized n-bit number to an m-bit number using shifters, adders, and subtractors to determine a pre-truncation value, which when truncated and expanded, minimizes error without requiring complex multiplication and division operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiplication and division operations are used to convert UNORM values between different bit lengths, then conversion accuracy is improved, but hardware complexity and silicon area increase
Solution Approach 1:
The patent changes the operational parameters from multiplication/division to addition/subtraction operations. Specifically, it uses the formula y = floor(x * (2^m - 0.5)) which can be implemented as y = (x << m) - (x >> (n-m-1)) - 1, transforming complex floating-point operations into simple integer arithmetic that is hardware-efficient while maintaining rounding accuracy.
Solution Approach 2:
The patent replaces the mechanical multiplication and division operations with bit shifting and addition/subtraction operations. This substitution uses the relationship between binary representation and powers of 2, where multiplication by 2^m becomes a left shift operation (x << m), and division by 2^k becomes a right shift operation (x >> k), eliminating the need for complex hardware multipliers and dividers.
2Device complexity
If simple truncation method is used to convert UNORM values, then hardware complexity is reduced, but conversion error increases
Solution Approach 1:
The patent applies preliminary correction to the input value before truncation. By adding the correction term (x >> (n-m-1)) + 1 to the shifted value (x << m) before performing the final subtraction and truncation, the method pre-compensates for the rounding error that would otherwise occur with simple truncation, ensuring the result is rounded to the nearest integer rather than simply truncated.
3Measurement precision
If complex rounding operations are implemented, then rounding accuracy is improved, but processing time increases
Solution Approach 1:
The patent replaces time-consuming multiplication and division operations with instantaneous bit shifting operations. In hardware, bit shifting is performed in a single clock cycle, whereas multiplication and division require multiple cycles or complex iterative algorithms. The formula y = (x << m) - (x >> (n-m-1)) - 1 can be executed in parallel using simple logic circuits, dramatically reducing processing time while maintaining rounding accuracy.
Data Source
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AI summary
A binary logic circuit and method are disclosed for rounding an unsigned normalised n-bit binary number to an m-bit binary number. A correction value of length of n bits and a pre-truncation value of length of n bits are determined. The correction value is determined by shifting the n-bit number by m bits. The pre-truncation value is determined based on at least the n-bit number, the correction value, a value for the most significant bit (MSB) of the n-bit number, and a rounding value having a '1' at the n-mth bit position and a '0' at all other bits. The rounded m-bit number is then obtained by truncating the n-m least significant bits (LSB) of the pre-truncation value.