Hardware Engine for TCP/IP Packet Processing

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Solution Overview

Problem

Current solutions for controlling communications between storage controllers and networks rely heavily on software-based implementations of the iSCSI protocol with the TCP/IP protocol stack, which are not sufficient to meet the high bandwidth requirements of modern and future network speeds.

Innovation Solution

A hardware engine-based system is introduced that processes TCP/IP data packets, including inbound and outbound MAC, IP, and TCP processing, with state machines for verification, reassembly, and transmission, to efficiently handle network data packets and improve processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If software-based implementations of the iSCSI protocol with the TCP/IP protocol stack are used, then ease of operation is improved, but processing speed deteriorates and cannot meet high bandwidth requirements

Engineering Contradiction:

Improveease of operationVSAvoidprocessing speed

Core Design Contradiction:

Ease of operationVSSpeed

Solution Approach 1:

The patent replaces the software-based TCP/IP protocol stack with a dedicated hardware engine that processes network data packets. This substitution of mechanical/software system with a hardware-based system enables the processor to meet high bandwidth requirements while maintaining ease of operation through automated hardware processing.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If software-based implementations are used, then device complexity is reduced, but productivity deteriorates and cannot handle high bandwidth requirements

Engineering Contradiction:

Improvedevice complexityVSAvoidproductivity

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent introduces a hardware engine to replace software-based processing, thereby increasing productivity to handle high bandwidth requirements. The hardware engine is designed with specific components for TCP/IP processing, balancing the increase in device complexity with significant gains in processing capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If hardware engine-based processing is implemented, then processing speed is improved, but device complexity increases

Engineering Contradiction:

Improveprocessing speedVSAvoiddevice complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The hardware engine is segmented into distinct functional components including an inbound processor with state machines for verifying and reassembling packets, and an outbound processor for transmitting packets. This segmentation allows each component to be optimized for its specific function while working together to achieve high processing speeds.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a buffer memory as an intermediary between the hardware engine and the processor. This buffer acts as a mediator that decouples the high-speed hardware processing from the slower software processing, allowing the hardware engine to operate at high speeds without overwhelming the main processor.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Ease of manufacture

If software-based implementations are used, then ease of manufacture is improved, but reliability deteriorates under high bandwidth conditions

Engineering Contradiction:

Improveease of manufactureVSAvoidreliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent replaces software-based TCP/IP processing with a dedicated hardware engine that provides reliable high-speed processing. The hardware engine includes built-in verification mechanisms such as state machines that verify inbound packets and ensure proper reassembly, enhancing reliability under high bandwidth conditions.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS7515612B1Method and system for processing network data packets

Publication Date: 2009.04.07 MARVELL ASIA PTE LTD

AI summary

A method for processing IP datagrams using an outbound processing state machine in an outbound processor, wherein the IP datagrams are generated by a host system is provided. The method includes, creating an IOCB with plural host memory addresses that define host data to be sent and a host memory address of a network control block (“NCB”) used to build network protocol headers, wherein the host sends the IOCB to the outbound processor. The outbound processor reads the NCB from host memory and creates an IP and MAC level protocol header(s) for a data packet(s) used to send the IP data. If a datagram fits into an IP packet, the outbound processor builds headers to send the datagram and then uses the plural host memory addresses defining the host data to read the data from the host, places the data into the packet and sends the packet.