Hardware Entitlement Registers for LPAR Resource Allocation

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Solution Overview

Problem

Current system virtualization technologies face challenges in efficiently managing processor resources among logical partitions (LPARs), leading to suboptimal utilization and increased context switching, as they rely on hypervisor-mediated resource allocation and time-sharing, which can result in inefficient execution and increased overhead.

Innovation Solution

The method involves using entitlement special purpose registers (ESPRs) to dedicate processor resources to each LPAR based on its specific requirements, allowing for direct hardware management of resource allocation and dispatching instructions without hypervisor intervention, ensuring each LPAR receives a specified percentage of execution time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If hypervisor-mediated resource allocation and time-sharing is used to manage processor resources among LPARs, then resource sharing and flexibility are improved, but processor resource utilization efficiency deteriorates and context switching increases

Engineering Contradiction:

Improveresource sharing flexibilityVSAvoidprocessor resource utilization efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts the resource allocation function from the software hypervisor layer and implements it directly in hardware through entitlement registers in the processor. This removes the intermediate software mediation layer that causes inefficiency, allowing direct hardware-enforced resource allocation while maintaining the ability to share resources among multiple LPARs.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces entitlement registers as a hardware intermediary between LPARs and processor resources. These registers store entitlement values that directly control resource allocation without requiring hypervisor intervention, thus eliminating the inefficiency of software-mediated time-sharing while preserving resource sharing capabilities.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If hypervisor-mediated resource allocation is used among multiple LPARs, then resource sharing capability is improved, but context switching overhead increases

Engineering Contradiction:

Improveresource sharing capabilityVSAvoidcontext switching overhead

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent removes the context switching function from the software hypervisor by implementing entitlement-based resource allocation in hardware. The entitlement registers directly control which LPAR receives processor access without requiring software context switches, thereby eliminating the time loss associated with hypervisor-mediated context switching while maintaining multi-LPAR resource sharing.

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If software-based hypervisor resource allocation is used, then system flexibility and resource sharing are improved, but execution efficiency and throughput deteriorate

Engineering Contradiction:

Improvesystem flexibilityVSAvoidexecution efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces the software-based (mechanical) hypervisor resource allocation system with a hardware-based entitlement register system. This substitution eliminates the overhead of software execution and context switching, directly improving execution efficiency and throughput while preserving system flexibility through configurable entitlement values in the hardware registers.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If time-shared processor allocation is used among LPARs, then resource utilization flexibility is improved, but processor overhead and execution latency increase

Engineering Contradiction:

Improveresource allocation flexibilityVSAvoidexecution latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent enables continuous processor execution for each LPAR by using hardware entitlement registers to directly control access without software intervention. This eliminates the discontinuities caused by hypervisor-mediated time-slicing and context switching, reducing execution latency while maintaining flexible resource allocation through configurable entitlement values.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10114673B2Honoring hardware entitlement of a hardware thread

Publication Date: 2018.10.30 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.