Hardware Event Prioritisation Module Offloads Processor Logic

The patent extracts the event queue management functionality from the processor software and implements it as a dedicated hardware module. This hardware module includes multiple event queues, priority assignment logic, and decision-making circuitry that operates independently of the processor, thereby freeing the processor from time-consuming queue management tasks while maintaining flexible event handling capabilities through configurable priority schemes and multiple event sources

The patent replaces the software-based mechanical decision-making process with hardware-based logic circuits. The hardware module implements priority encoding circuits, comparison logic, and selection mechanisms that automatically determine which event to process next based on predefined priority levels. This substitution eliminates the time delays associated with software execution while maintaining complex decision-making capabilities through hardware-configurable priority schemes and multi-criteria evaluation logic

The patent segments the event handling system into dedicated hardware components: separate event queues for different event sources, individual priority assignment units for each queue, and a centralized decision-making logic. This segmentation allows each component to operate independently and efficiently, processing only relevant events from its assigned source. The hardware implementation of each segment consumes significantly fewer processing resources compared to a unified software-based approach, while collectively maintaining comprehensive event source coverage through modular scalability