Hardware Event Processing Unit for Low Latency Interconnect

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Solution Overview

Problem

Current event handling in operating systems involves significant software processing, leading to high and unpredictable latency due to the need for processor intervention in managing events, which diverts resources away from application execution and introduces variability in processing times.

Innovation Solution

Integration of a processor instruction set, interrupt controller, and hardware queue management to handle events without operating system intervention, allowing for deterministic latency and efficient processor cycles allocation to application work, with the introduction of instructions like 'Wait for Next Event' (WNE) and 'HANDOFF' to manage event processing in hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If operating system software processing is used to handle events, then events can be managed with flexible scheduling and process control, but significant processor cycles are consumed and latency becomes high and unpredictable

Engineering Contradiction:
Improveevent handling correctnessVSAvoidevent latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the mechanical software-based event handling system with a hardware-based event processing system. The event processing unit (EPU) is implemented as hardware that can directly receive, process, and route events without requiring operating system software intervention. This substitution eliminates the time-consuming software execution path while maintaining correct event handling through dedicated hardware logic that mirrors the software's event management functionality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an event processing unit (EPU) as an intermediary component between the event source and the operating system. The EPU acts as a mediator that pre-processes events in hardware, filtering and routing them before they reach the software layer. This intermediary handles the time-critical event processing in hardware while allowing the OS to maintain control over higher-level scheduling and management tasks.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If operating system software processing is used to handle events, then comprehensive event management and scheduling is achieved, but processor cycles are diverted from application execution

Engineering Contradiction:
Improveevent management capabilityVSAvoidapplication execution efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the event handling functionality into two distinct parts: a hardware-based event processing unit (EPU) that handles time-critical event reception and initial processing, and the software-based operating system that handles higher-level scheduling and management. This segmentation allows the hardware EPU to handle events with minimal processor intervention, freeing up CPU cycles for application execution while the OS retains adaptability through its software-based event management capabilities.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If traditional interrupt handling is used, then events can be processed with standard OS mechanisms, but context switches and interrupts increase processing overhead

Engineering Contradiction:
Improvestandard OS event handlingVSAvoidprocessing overhead
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent replaces the traditional software-based interrupt handling mechanism with a hardware-based event processing unit. Instead of relying on standard OS interrupt routines that require context switches and software execution, the EPU processes events directly in hardware, eliminating the overhead associated with traditional interrupt handling while maintaining ease of operation through standardized interfaces to the operating system.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9921891B1Low latency interconnect integrated event handling
Publication Date: 2018.03.20 AXIRO SEMICONDUCTOR INC
  • US9921891B1 patent drawing
  • US9921891B1 patent drawing
  • US9921891B1 patent drawing

AI summary

Low Latency Interconnect Integrated Event Handling has been disclosed. In one implementation a hardware based interrupt controller coupled with a hardware based event queue manager, dedicated hardware based queues, and processor instruction extensions allows for off-loading event processing from an operating system thereby dramatically lowering wasted processor cycles while speeding up event processing.