Hardware Exception Control Circuitry for Secure Domain Transitions
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Solution Overview
Problem
Current data processing systems face a trade-off between security and performance, particularly in small systems like microcontrollers, where secure and non-secure domains require significant software intervention, leading to performance overhead and increased development complexity.
Innovation Solution
A data processing apparatus with exception control circuitry that performs state saving of registers in hardware before transitioning from a secure domain to a less secure domain, allowing the exception handling routine to focus on software tasks without proxying through a secure exception handler, thereby reducing performance impact and maintaining security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a software handler is used to transition between secure and non-secure states, then security is protected, but performance is reduced and development effort increases
Solution Approach 1:
The patent replaces the software-based exception handling mechanism with a hardware-based mechanism. The secure exception handler circuitry is implemented in hardware within the secure domain, allowing direct handling of exceptions without requiring software intervention or proxying through non-secure domain handlers. This hardware implementation eliminates the performance overhead and development complexity associated with software handlers while maintaining security boundaries.
2Reliability
If all exception calls are proxied through a secure exception handler, then security is maintained, but development complexity increases
Solution Approach 1:
The patent extracts the secure exception handling functionality from the software domain and implements it as dedicated hardware circuitry. This extraction allows the secure exception handler to operate independently in hardware, removing the requirement for software developers to create proxy handlers for every exception. The hardware circuitry automatically manages secure exception transitions, significantly reducing API development effort while maintaining security.
3Reliability
If state saving is performed in software for all registers, then security is maintained, but processing delay increases
Solution Approach 1:
The patent replaces software-based state saving operations with hardware-based automatic state saving. The secure exception handler circuitry includes hardware mechanisms that automatically save and restore register states during exception transitions. This hardware implementation performs state saving in parallel with exception handling, eliminating the sequential software overhead and reducing processing delays while ensuring secure data is properly saved before transitioning to non-secure domain handling.
Data Source
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Figure 3A~3B
AI summary
Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.