Hardware Feedback Tables for Virtual Machine Core Scheduling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In virtual environments, the lack of hardware feedback information to virtual machines leads to inefficient scheduling of threads on hybrid processor cores, resulting in suboptimal performance and increased complexity due to incorrect mapping of virtual processors to physical cores.

Innovation Solution

Providing hardware feedback information directly to virtual machines through HGS feedback tables, allowing them to make informed scheduling decisions based on the dynamic performance and efficiency of physical cores, thereby reducing the need for frequent reshuffling by the root partition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hardware feedback information is provided only to the root partition (not to virtual machines), then the root partition can schedule threads effectively based on hardware state, but virtual machines cannot make informed scheduling decisions leading to incorrect mapping of virtual processors to physical cores

Engineering Contradiction:
Improvethread scheduling efficiencyVSAvoidcomplexity of virtual processor to physical core mapping
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces HGS feedback tables as an intermediary mechanism that bridges the hardware feedback interface and virtual machines. These tables store hardware feedback information (performance and efficiency metrics) in a format accessible to both the root partition and virtual machines, enabling informed scheduling decisions at both levels without increasing overall system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the hardware feedback information access by creating separate HGS feedback table instances for the root partition and each virtual machine. This segmentation allows each entity to access relevant hardware state information independently, enabling virtual machines to make autonomous scheduling decisions while the root partition maintains overall system coordination

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If virtual machines schedule threads without hardware feedback information, then the scheduling process is simpler, but the mapping of virtual processors to physical cores becomes incorrect leading to suboptimal performance

Engineering Contradiction:
Improvescheduling decision makingVSAvoidsystem performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where hardware feedback information (performance and efficiency metrics from monitor circuits) is stored in HGS feedback tables and made accessible to virtual machines. This feedback enables virtual machine schedulers to make informed decisions about thread-to-core mapping based on actual hardware state, improving both ease of operation and system performance

Inventive Principle:
Principle #23Feedback

3Productivity

If the root partition frequently reshuffles virtual processor to physical core mappings to optimize performance, then system performance improves, but the complexity and overhead of management increases

Engineering Contradiction:
Improvesystem performanceVSAvoidcomplexity of root partition scheduling management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent enables virtual machines to perform preliminary scheduling actions by providing them with hardware feedback information through HGS feedback tables. Virtual machines can pre-optimize their thread-to-core mappings based on hardware state before the root partition needs to intervene, reducing the frequency and complexity of reshuffling operations required by the root partition

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240152373A1Providing hardware feedback information in a virtual environment
Publication Date: 2024.05.09 INTEL CORP
  • US20240152373A1 patent drawing
  • US20240152373A1 patent drawing
  • US20240152373A1 patent drawing

AI summary

In one embodiment, a method includes: receiving, in a first circuit of a processor, an indication of an entry of the processor into a first virtual machine, the processor to execute in a virtual machine environment having a root partition and at least one virtual partition comprising the first virtual machine; allocating a first hardware feedback structure for the root partition and allocating a second hardware feedback structure for the at least one virtual partition; populating the first hardware feedback structure with first performance and efficiency information regarding a plurality of cores of the processor; populating the second hardware feedback structure with the first performance and efficiency information regarding the plurality of cores of the processor; and providing the first performance and efficiency information from the second hardware feedback structure to a virtual machine scheduler of the at least one virtual partition. Other embodiments are described and claimed.