Hardware FIB Selector Block for Constant-Time MPLS Rerouting
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Solution Overview
Problem
Existing network routing technologies face delays and increased packet loss when rerouting Label Switched Paths (LSPs) due to link failures, as the time required to update forwarding information base (FIB) entries is proportional to the number of LSPs sharing the failed link, leading to scalability issues.
Innovation Solution
A hardware-based FIB is programmed into a packet-forwarding engine's ASIC, including primary and backup next hops, with a selector block that automatically switches to backup next hops upon link failure, independent of the number of LSPs, allowing for constant time rerouting without the need for extensive control plane signaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control plane signaling is used to rewrite FIB entries to switch to bypass tunnel, then routing flexibility is improved, but rerouting time increases proportionally with the number of LSPs
Solution Approach 1:
The patent pre-configures backup next hops and detour tunnels in the hardware FIB before link failures occur. Selector blocks are pre-programmed with alternative routing paths, enabling immediate switching upon failure without requiring time-consuming control plane signaling or FIB rewriting operations.
Solution Approach 2:
The patent replaces the software-based control plane signaling mechanism with a hardware-based selection mechanism in the packet-forwarding engine. The selector blocks use hardware-controlled switching based on link status signals, eliminating the need for iterative control plane communication and FIB updates for each LSP.
2Speed
If hardware-based FIB with selector blocks is used, then rerouting speed is improved, but device complexity increases
Solution Approach 1:
The selector blocks serve multiple functions: they monitor link status, store backup next hop information, and control packet forwarding decisions. This multi-functionality reduces the need for separate dedicated components for each function, thereby managing hardware complexity while achieving fast rerouting.
Solution Approach 2:
The patent combines the backup next hop storage, link status monitoring, and forwarding decision logic into integrated selector blocks within the hardware FIB. This consolidation reduces the number of separate components and interconnections needed, managing device complexity while enabling rapid switching.
3Reliability
If extensive control plane signaling is used for FIB updates, then routing accuracy is improved, but packet loss increases during link failures
Solution Approach 1:
Backup routing information is pre-loaded into the hardware FIB selector blocks before failures occur. When a link failure is detected, the hardware automatically switches to pre-configured backup paths without waiting for control plane signaling, eliminating packet loss during the switching transition while maintaining routing accuracy through pre-validated backup paths.
4Ease of operation
If software-based FIB updates are used, then routing control is improved, but scalability deteriorates with increasing number of LSPs
Solution Approach 1:
The patent replaces software-based FIB update mechanisms with hardware-based selector block control. The hardware automatically manages routing decisions based on link status signals, eliminating the scalability bottleneck of software processing while maintaining routing control through configurable selector block programming.
Data Source
AI summary
Techniques are described for maintaining a forwarding information base (FIB) within a packet-forwarding engine (PFE) of a router, and programming a packet-forwarding integrated circuit (IC) with a hardware version of the FIB. Entries of the hardware version identify primary forwarding next hops and backup forwarding next hops for the LSPs, wherein the packet-forwarding IC includes a control logic module and internal selector block configured to produce a value indicating a state of the first physical link. The selector block outputs one of the primary forwarding next hop and the backup forwarding next hop of the entries for forwarding the MPLS packets based on the value in response to the packet-processing engine addressing one of the entries of the FIB for the LSPs. Packets are forwarded with the PFE to the one of the primary forwarding next hop and the backup forwarding next hop output by the selector block.


