Hardware Frequency Control for Lower-Voltage Processor Core Operation
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Solution Overview
Problem
Existing computing devices inefficiently consume power due to operating processor cores at frequencies that are either higher or lower than necessary to meet performance criteria, resulting in excessive voltage levels.
Innovation Solution
A frequency control circuit that cycles the operating frequency of processor cores between two frequencies associated with the nearest supported DCVS levels, aligning transitions to reduce power consumption and maintain an average frequency that meets performance criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor core is operated at a frequency associated with a DCVS level having a voltage level that satisfies a voltage criterion, then the voltage criterion is satisfied, but the power consumption is inefficient due to higher than needed voltage levels
Solution Approach 1:
The system dynamically switches between two DCVS levels (first and second levels) based on performance requirements. Instead of operating at a single fixed frequency, the processor core alternates between a higher frequency (first DCVS level) and a lower frequency (second DCVS level), allowing the average operating frequency to match the target frequency while reducing overall power consumption.
Solution Approach 2:
The frequency control circuit implements periodic switching between the first and second DCVS levels. This periodic action allows the system to achieve the target average frequency over time while minimizing the time spent at higher voltage levels, thereby reducing power consumption while still satisfying performance criteria.
2Use of energy by moving object
If the processor core is operated at a lower frequency to reduce power consumption, then power consumption is reduced, but the performance criterion may not be satisfied
Solution Approach 1:
The system uses dynamic frequency switching between two DCVS levels to achieve the target average frequency. By alternating between higher and lower frequencies, the system ensures that performance requirements are met on average while reducing power consumption compared to operating continuously at the higher frequency.
Solution Approach 2:
The system changes the operating frequency parameter dynamically by switching between two discrete frequency levels. This parameter change strategy allows the system to achieve the desired average frequency (matching the target) while operating at lower power consumption levels for portions of the time.
3Device complexity
If a limited number of DCVS levels are supported to reduce complexity, then device complexity is reduced, but the frequency granularity is insufficient to operate closer to target frequencies
Solution Approach 1:
The system segments the frequency control into two distinct DCVS levels (first and second levels) with a frequency control circuit that manages the switching between them. This segmentation approach provides sufficient frequency granularity to achieve target frequencies while keeping the overall system complexity low by limiting the number of DCVS levels to two.
Solution Approach 2:
The frequency control circuit acts as an intermediary that manages the switching between the two DCVS levels. This intermediary component enables precise frequency control and achieves target frequencies by coordinating the transitions between levels, effectively bridging the gap between limited DCVS levels and precise frequency requirements.
Data Source
AI summary
A device includes a processor core and a frequency control circuit. The frequency control circuit is configured to obtain a signal based on a target frequency for the processor core. The frequency control circuit is also configured, based on the signal, to cause an operating frequency of the processor core to cycle between a first frequency greater than the target frequency and a second frequency less than the target frequency.