Hardware Hash Circuit for Secure Fixed-Length Data Reduction
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Solution Overview
Problem
Conventional software-implemented hash algorithms are vulnerable to deciphering, leading to security issues due to the lack of physical isolation and hardware-based security measures.
Innovation Solution
A hash algorithm circuit with a hardware structure that reduces fixed-length parallel data using a combination of exclusive OR, summation, and shift circuits, arranged according to preset hash algorithms such as direct addressing, digital analysis, middle-square, folding, and division-remainder methods, to form a target data with a shorter length, making it difficult to reverse-engineer the original input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hash algorithm is implemented by software, then flexibility and ease of modification are improved, but security is worsened due to lack of physical isolation and vulnerability to deciphering
Solution Approach 1:
The patent replaces the software-based hash algorithm implementation with a hardware circuit implementation. The hash algorithm is transformed into a physical circuit structure comprising logic gates, registers, and computational units that perform hash operations through electrical signals and physical logic operations, providing physical isolation and resistance to deciphering while maintaining functional capability
Solution Approach 2:
The patent changes the implementation medium parameter from software (virtual execution) to hardware (physical circuit). This parameter change fundamentally alters the security characteristics by introducing physical isolation, making the hash algorithm resistant to software-based attacks and deciphering attempts while preserving the core hash computation functionality
2Quantity of substance
If data is compressed into fixed-length hash value, then storage efficiency is improved, but information recovery capability is worsened as unique input cannot be determined from hash value
Solution Approach 1:
The patent extracts only the essential features of the input data to create a fixed-length hash value, deliberately discarding redundant information. This extraction process achieves compression and storage efficiency while the one-way nature of the extraction ensures that the original input cannot be recovered, which is the desired security property for hash functions
Solution Approach 2:
The patent converts the inherent information loss in compression into a security benefit. The irreversibility of the hash function, which initially appears as information loss, is transformed into a protective feature that prevents deciphering and ensures data integrity, making the 'harm' of information loss into the 'blessing' of security
3Reliability
If hardware circuit structure is used for hash algorithm, then security is improved through physical isolation, but device complexity is worsened
Solution Approach 1:
The patent segments the hash algorithm into distinct functional circuit modules including compression function units, message schedule registers, and logic gate layers. Each module performs a specific part of the hash computation, making the overall complex circuit manageable, testable, and implementable through systematic modular design
Solution Approach 2:
The patent designs universal circuit components that can perform multiple operations within the hash algorithm. For example, the logic gates and registers are configured to handle different stages of the hash computation (compression, mixing, permutation), reducing the total number of dedicated components needed and simplifying the overall circuit structure while maintaining security
Data Source
AI summary
The present disclosure provides a hash algorithm circuit, a hash algorithm method, and an electronic device. The hash algorithm circuit is used to reduce fixed-length parallel data, and the reduced identifier can be used as an index reference, an identifier ID, an address extension bit, information summary, and so on. The hash algorithm circuit has the characteristics of low power consumption, low cost, etc., and can be integrated in a digital circuit.