Hardware Instruction Segmentation for Chip Area Reduction
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Solution Overview
Problem
Existing processor architectures require larger chip areas and reduced pipelining and functional parallelism when performing mathematical functions using monolithic hardware instructions, and functional verification of these instructions is costly due to numerous inputs to be tested.
Innovation Solution
Implementing a method that includes performing hardware reduction and restoration instructions to calculate range reduction and restoration factors, followed by a final fused multiply add (FMA) or floating-point multiply (FM) instruction, which allows for pipelined execution and reduced chip area usage by separating operations into distinct instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mathematical functions are performed using monolithic hardware instructions, then functional correctness is ensured, but chip area increases and pipelining opportunities are reduced
Solution Approach 1:
The monolithic hardware instruction is divided into multiple separate instructions: a reduction instruction that calculates a range reduction factor, a restoration instruction that calculates a range restoration factor, and a final FMA or FM instruction that combines results. This segmentation reduces the area required for each individual instruction while maintaining overall functional correctness through coordinated execution of the split operations.
2Reliability
If mathematical functions are performed using monolithic hardware instructions, then functional correctness is ensured, but pipelining and functional parallelism are reduced
Solution Approach 1:
By splitting the monolithic instruction into multiple independent instructions (reduction, restoration, and final computation), the patent enables pipelining where different stages can process different inputs simultaneously. The reduction instruction can operate on one input while the restoration instruction operates on another, increasing functional parallelism and throughput.
3Area of stationary object
If hardware instructions are separated into distinct operations, then chip area is reduced and pipelining is enabled, but functional verification becomes more complex
Solution Approach 1:
While segmentation creates multiple instructions, each with simpler individual verification requirements, the patent maintains functional correctness by ensuring each segmented instruction performs a well-defined operation (reduction factor calculation, restoration factor calculation, final combination). This modular structure actually simplifies verification compared to a monolithic instruction, as each component can be verified independently.
Data Source
AI summary
A method, computer program product, and a computer system are disclosed for processing information using hardware instructions in a processor of a computer system by performing a hardware reduction instruction using an input to calculate at least one range reduction factor of the input; performing a hardware restoration instruction using the input to calculate at least one range restoration factor of the input; and performing a final fused multiply add (FMA) type of hardware instruction or a multiply (FM) hardware instruction by combining an approximation based on a value reduced by the at least one range reduction factor with the at least one range restoration factor.