Hardware Instruction Translator for x86 ARM Microprocessor
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Solution Overview
Problem
Computing device manufacturers and users face challenges in running both x86 and ARM architecture programs due to the dominance of one architecture over the other, leading to wasted investments and the need for devices that can support multiple instruction sets.
Innovation Solution
A microprocessor with a hardware instruction translator that translates x86 and ARM instructions into microinstructions, executed by an out-of-order execution pipeline, allowing for conditional load/store instructions based on condition flags, enabling the execution of both x86 and ARM machine language programs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a microprocessor supports both x86 and ARM instruction sets through hardware translation, then versatility and adaptability improve, but device complexity increases
Solution Approach 1:
The microprocessor is designed to execute both x86 and ARM instruction sets on a single device, eliminating the need for separate processors. The hardware instruction translator enables the same physical device to universally support multiple instruction set architectures, allowing users to run software developed for different architectures without requiring separate hardware systems.
Solution Approach 2:
A hardware instruction translator is introduced as an intermediary component between the executed instruction set and the execution pipeline. This translator mediates between the x86 or ARM instructions and the microprocessor's internal execution architecture, converting instructions from different ISAs into executable microinstructions without requiring multiple separate execution paths.
2Productivity
If hardware instruction translation is used instead of software translation, then execution speed and productivity improve, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent replaces software-based translation mechanisms with a hardware-based instruction translator. Instead of using software to interpret and execute instructions, the hardware translator directly converts x86 or ARM instructions into executable microinstructions at the hardware level, enabling parallel translation and execution that significantly improves speed compared to sequential software interpretation.
Solution Approach 2:
The instruction translation process is segmented into distinct hardware components: an instruction translator that converts ISA instructions into microinstructions, a microinstruction cache that stores frequently accessed translations, and an execution pipeline that processes the microinstructions. This segmentation allows each component to be optimized independently and enables concurrent operation of multiple translation and execution units.
3Adaptability or versatility
If conditional load/store instructions are translated into variable numbers of microinstructions, then execution flexibility and adaptability improve, but the number of microinstruction types and complexity increase
Solution Approach 1:
The instruction translator dynamically determines the number of microinstructions needed to implement each conditional load/store instruction based on the specific addressing mode and condition flags. Rather than using a fixed translation scheme, the system adapts the microinstruction sequence length and content according to the runtime conditions and instruction parameters, allowing flexible handling of various memory access patterns.
Solution Approach 2:
The translation of conditional load/store instructions utilizes parameter changes in the microinstruction format to handle different addressing modes and condition combinations. By varying parameters such as the number of microinstructions, the destination register, source register, memory address, and condition code within the microinstruction set, the system can represent multiple instruction variants without requiring separate microinstruction types for each case.
Data Source
AI summary
An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.